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Commit 796e1c55 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'drm-next' of git://people.freedesktop.org/~airlied/linux 

Pull drm updates from Dave Airlie:
 "This is the main drm pull, it has a shared branch with some alsa
  crossover but everything should be acked by relevant people.

  New drivers:
     - ATMEL HLCDC driver
     - designware HDMI core support (used in multiple SoCs).

  core:
     - lots more atomic modesetting work, properties and atomic ioctl
       (hidden under option)
     - bridge rework allows support for Samsung exynos chromebooks to
       work finally.
     - some more panels supported

  i915:
     - atomic plane update support
     - DSI uses shared DSI infrastructure
     - Skylake basic support is all merged now
     - component framework used for i915/snd-hda interactions
     - write-combine cpu memory mappings
     - engine init code refactored
     - full ppgtt enabled where execlists are enabled.
     - cherryview rps/gpu turbo and pipe CRC support.

  radeon:
     - indirect draw support for evergreen/cayman
     - SMC and manual fan control for SI/CI
     - Displayport audio support

  amdkfd:
     - SDMA usermode queue support
     - replace suballocator usage with more suitable one
     - rework for allowing interfacing to more than radeon

  nouveau:
     - major renaming in prep for later splitting work
     - merge arm platform driver into nouveau
     - GK20A reclocking support

  msm:
     - conversion to atomic modesetting
     - YUV support for mdp4/5
     - eDP support
     - hw cursor for mdp5

  tegra:
     - conversion to atomic modesetting
     - better suspend/resume support for child devices

  rcar-du:
     - interlaced support

  imx:
     - move to using dw_hdmi shared support
     - mode_fixup support

  sti:
     - DVO support
     - HDMI infoframe support

  exynos:
     - refactoring and cleanup, removed lots of internal unnecessary
       abstraction
     - exynos7 DECON display controller support

  Along with the usual bunch of fixes, cleanups etc"

* 'drm-next' of git://people.freedesktop.org/~airlied/linux: (724 commits)
  drm/radeon: fix voltage setup on hawaii
  drm/radeon/dp: Set EDP_CONFIGURATION_SET for bridge chips if necessary
  drm/radeon: only enable kv/kb dpm interrupts once v3
  drm/radeon: workaround for CP HW bug on CIK
  drm/radeon: Don't try to enable write-combining without PAT
  drm/radeon: use 0-255 rather than 0-100 for pwm fan range
  drm/i915: Clamp efficient frequency to valid range
  drm/i915: Really ignore long HPD pulses on eDP
  drm/exynos: Add DECON driver
  drm/i915: Correct the base value while updating LP_OUTPUT_HOLD in MIPI_PORT_CTRL
  drm/i915: Insert a command barrier on BLT/BSD cache flushes
  drm/i915: Drop vblank wait from intel_dp_link_down
  drm/exynos: fix NULL pointer reference
  drm/exynos: remove exynos_plane_dpms
  drm/exynos: remove mode property of exynos crtc
  drm/exynos: Remove exynos_plane_dpms() call with no effect
  drm/i915: Squelch overzealous uncore reset WARN_ON
  drm/i915: Take runtime pm reference on hangcheck_info
  drm/i915: Correct the IOSF Dev_FN field for IOSF transfers
  drm/exynos: fix DMA_ATTR_NO_KERNEL_MAPPING usage
  ...
parents 8c334ce8 45ee2dbc

Documentation/DocBook/drm.tmpl

+122 −4
Original line number Diff line number Diff line
@@ -239,6 +239,14 @@ 
              Driver supports dedicated render nodes.

            </para></listitem>

          </varlistentry>

          <varlistentry>

            <term>DRIVER_ATOMIC</term>

            <listitem><para>

              Driver supports atomic properties.  In this case the driver

              must implement appropriate obj->atomic_get_property() vfuncs

              for any modeset objects with driver specific properties.

            </para></listitem>

          </varlistentry>

        </variablelist>

      </sect3>

      <sect3>
@@ -1377,7 +1385,7 @@ int max_width, max_height;</synopsis> 
      <itemizedlist>

        <listitem>

        DRM_PLANE_TYPE_PRIMARY represents a "main" plane for a CRTC.  Primary

        planes are the planes operated upon by by CRTC modesetting and flipping

        planes are the planes operated upon by CRTC modesetting and flipping

        operations described in <xref linkend="drm-kms-crtcops"/>.

        </listitem>

        <listitem>
@@ -2362,6 +2370,7 @@ void intel_crt_init(struct drm_device *dev) 
    </sect2>

    <sect2>

      <title>Modeset Helper Functions Reference</title>

!Iinclude/drm/drm_crtc_helper.h

!Edrivers/gpu/drm/drm_crtc_helper.c

!Pdrivers/gpu/drm/drm_crtc_helper.c overview

    </sect2>
@@ -2564,8 +2573,8 @@ void intel_crt_init(struct drm_device *dev) 
	<td valign="top" >Description/Restrictions</td>

	</tr>

	<tr>

	<td rowspan="25" valign="top" >DRM</td>

	<td rowspan="4" valign="top" >Generic</td>

	<td rowspan="36" valign="top" >DRM</td>

	<td rowspan="5" valign="top" >Connector</td>

	<td valign="top" >“EDID”</td>

	<td valign="top" >BLOB | IMMUTABLE</td>

	<td valign="top" >0</td>
@@ -2594,7 +2603,14 @@ void intel_crt_init(struct drm_device *dev) 
	<td valign="top" >Contains tiling information for a connector.</td>

	</tr>

	<tr>

	<td rowspan="1" valign="top" >Plane</td>

	<td valign="top" >“CRTC_ID”</td>

	<td valign="top" >OBJECT</td>

	<td valign="top" >DRM_MODE_OBJECT_CRTC</td>

	<td valign="top" >Connector</td>

	<td valign="top" >CRTC that connector is attached to (atomic)</td>

	</tr>

	<tr>

	<td rowspan="11" valign="top" >Plane</td>

	<td valign="top" >“type”</td>

	<td valign="top" >ENUM | IMMUTABLE</td>

	<td valign="top" >{ "Overlay", "Primary", "Cursor" }</td>
@@ -2602,6 +2618,76 @@ void intel_crt_init(struct drm_device *dev) 
	<td valign="top" >Plane type</td>

	</tr>

	<tr>

	<td valign="top" >“SRC_X”</td>

	<td valign="top" >RANGE</td>

	<td valign="top" >Min=0, Max=UINT_MAX</td>

	<td valign="top" >Plane</td>

	<td valign="top" >Scanout source x coordinate in 16.16 fixed point (atomic)</td>

	</tr>

	<tr>

	<td valign="top" >“SRC_Y”</td>

	<td valign="top" >RANGE</td>

	<td valign="top" >Min=0, Max=UINT_MAX</td>

	<td valign="top" >Plane</td>

	<td valign="top" >Scanout source y coordinate in 16.16 fixed point (atomic)</td>

	</tr>

	<tr>

	<td valign="top" >“SRC_W”</td>

	<td valign="top" >RANGE</td>

	<td valign="top" >Min=0, Max=UINT_MAX</td>

	<td valign="top" >Plane</td>

	<td valign="top" >Scanout source width in 16.16 fixed point (atomic)</td>

	</tr>

	<tr>

	<td valign="top" >“SRC_H”</td>

	<td valign="top" >RANGE</td>

	<td valign="top" >Min=0, Max=UINT_MAX</td>

	<td valign="top" >Plane</td>

	<td valign="top" >Scanout source height in 16.16 fixed point (atomic)</td>

	</tr>

	<tr>

	<td valign="top" >“CRTC_X”</td>

	<td valign="top" >SIGNED_RANGE</td>

	<td valign="top" >Min=INT_MIN, Max=INT_MAX</td>

	<td valign="top" >Plane</td>

	<td valign="top" >Scanout CRTC (destination) x coordinate (atomic)</td>

	</tr>

	<tr>

	<td valign="top" >“CRTC_Y”</td>

	<td valign="top" >SIGNED_RANGE</td>

	<td valign="top" >Min=INT_MIN, Max=INT_MAX</td>

	<td valign="top" >Plane</td>

	<td valign="top" >Scanout CRTC (destination) y coordinate (atomic)</td>

	</tr>

	<tr>

	<td valign="top" >“CRTC_W”</td>

	<td valign="top" >RANGE</td>

	<td valign="top" >Min=0, Max=UINT_MAX</td>

	<td valign="top" >Plane</td>

	<td valign="top" >Scanout CRTC (destination) width (atomic)</td>

	</tr>

	<tr>

	<td valign="top" >“CRTC_H”</td>

	<td valign="top" >RANGE</td>

	<td valign="top" >Min=0, Max=UINT_MAX</td>

	<td valign="top" >Plane</td>

	<td valign="top" >Scanout CRTC (destination) height (atomic)</td>

	</tr>

	<tr>

	<td valign="top" >“FB_ID”</td>

	<td valign="top" >OBJECT</td>

	<td valign="top" >DRM_MODE_OBJECT_FB</td>

	<td valign="top" >Plane</td>

	<td valign="top" >Scanout framebuffer (atomic)</td>

	</tr>

	<tr>

	<td valign="top" >“CRTC_ID”</td>

	<td valign="top" >OBJECT</td>

	<td valign="top" >DRM_MODE_OBJECT_CRTC</td>

	<td valign="top" >Plane</td>

	<td valign="top" >CRTC that plane is attached to (atomic)</td>

	</tr>

	<tr>

	<td rowspan="2" valign="top" >DVI-I</td>

	<td valign="top" >“subconnector”</td>

	<td valign="top" >ENUM</td>
@@ -3883,6 +3969,7 @@ int num_ioctls;</synopsis> 
        <title>Runtime Power Management</title>

!Pdrivers/gpu/drm/i915/intel_runtime_pm.c runtime pm

!Idrivers/gpu/drm/i915/intel_runtime_pm.c

!Idrivers/gpu/drm/i915/intel_uncore.c

      </sect2>

      <sect2>

        <title>Interrupt Handling</title>
@@ -3931,6 +4018,11 @@ int num_ioctls;</synopsis> 
	  framebuffer compression and panel self refresh.

        </para>

      </sect2>

      <sect2>

        <title>Atomic Plane Helpers</title>

!Pdrivers/gpu/drm/i915/intel_atomic_plane.c atomic plane helpers

!Idrivers/gpu/drm/i915/intel_atomic_plane.c

      </sect2>

      <sect2>

        <title>Output Probing</title>

        <para>
@@ -3949,6 +4041,11 @@ int num_ioctls;</synopsis> 
	<title>Panel Self Refresh PSR (PSR/SRD)</title>

!Pdrivers/gpu/drm/i915/intel_psr.c Panel Self Refresh (PSR/SRD)

!Idrivers/gpu/drm/i915/intel_psr.c

      </sect2>

      <sect2>

	<title>Frame Buffer Compression (FBC)</title>

!Pdrivers/gpu/drm/i915/intel_fbc.c Frame Buffer Compression (FBC)

!Idrivers/gpu/drm/i915/intel_fbc.c

      </sect2>

      <sect2>

        <title>DPIO</title>
@@ -4052,12 +4149,33 @@ int num_ioctls;</synopsis> 
        <title>Batchbuffer Parsing</title>

!Pdrivers/gpu/drm/i915/i915_cmd_parser.c batch buffer command parser

!Idrivers/gpu/drm/i915/i915_cmd_parser.c

      </sect2>

      <sect2>

        <title>Batchbuffer Pools</title>

!Pdrivers/gpu/drm/i915/i915_gem_batch_pool.c batch pool

!Idrivers/gpu/drm/i915/i915_gem_batch_pool.c

      </sect2>

      <sect2>

        <title>Logical Rings, Logical Ring Contexts and Execlists</title>

!Pdrivers/gpu/drm/i915/intel_lrc.c Logical Rings, Logical Ring Contexts and Execlists

!Idrivers/gpu/drm/i915/intel_lrc.c

      </sect2>

      <sect2>

        <title>Global GTT views</title>

!Pdrivers/gpu/drm/i915/i915_gem_gtt.c Global GTT views

!Idrivers/gpu/drm/i915/i915_gem_gtt.c

      </sect2>

      <sect2>

        <title>Buffer Object Eviction</title>

	<para>

	  This section documents the interface function for evicting buffer

	  objects to make space available in the virtual gpu address spaces.

	  Note that this is mostly orthogonal to shrinking buffer objects

	  caches, which has the goal to make main memory (shared with the gpu

	  through the unified memory architecture) available.

	</para>

!Idrivers/gpu/drm/i915/i915_gem_evict.c

      </sect2>

    </sect1>



    <sect1>

Documentation/devicetree/bindings/drm/atmel/hlcdc-dc.txt

0 → 100644
+53 −0
Original line number Diff line number Diff line 
Device-Tree bindings for Atmel's HLCDC (High LCD Controller) DRM driver



The Atmel HLCDC Display Controller is subdevice of the HLCDC MFD device.

See ../mfd/atmel-hlcdc.txt for more details.



Required properties:

 - compatible: value should be "atmel,hlcdc-display-controller"

 - pinctrl-names: the pin control state names. Should contain "default".

 - pinctrl-0: should contain the default pinctrl states.

 - #address-cells: should be set to 1.

 - #size-cells: should be set to 0.



Required children nodes:

 Children nodes are encoding available output ports and their connections

 to external devices using the OF graph reprensentation (see ../graph.txt).

 At least one port node is required.



Example:



	hlcdc: hlcdc@f0030000 {

		compatible = "atmel,sama5d3-hlcdc";

		reg = <0xf0030000 0x2000>;

		interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>;

		clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>;

		clock-names = "periph_clk","sys_clk", "slow_clk";

		status = "disabled";



		hlcdc-display-controller {

			compatible = "atmel,hlcdc-display-controller";

			pinctrl-names = "default";

			pinctrl-0 = <&pinctrl_lcd_base &pinctrl_lcd_rgb888>;

			#address-cells = <1>;

			#size-cells = <0>;



			port@0 {

				#address-cells = <1>;

				#size-cells = <0>;

				reg = <0>;



				hlcdc_panel_output: endpoint@0 {

					reg = <0>;

					remote-endpoint = <&panel_input>;

				};

			};

		};



		hlcdc_pwm: hlcdc-pwm {

			compatible = "atmel,hlcdc-pwm";

			pinctrl-names = "default";

			pinctrl-0 = <&pinctrl_lcd_pwm>;

			#pwm-cells = <3>;

		};

	};

Documentation/devicetree/bindings/drm/bridge/dw_hdmi.txt

0 → 100644
+50 −0
Original line number Diff line number Diff line 
DesignWare HDMI bridge bindings



Required properties:

- compatible: platform specific such as:

   * "snps,dw-hdmi-tx"

   * "fsl,imx6q-hdmi"

   * "fsl,imx6dl-hdmi"

   * "rockchip,rk3288-dw-hdmi"

- reg: Physical base address and length of the controller's registers.

- interrupts: The HDMI interrupt number

- clocks, clock-names : must have the phandles to the HDMI iahb and isfr clocks,

  as described in Documentation/devicetree/bindings/clock/clock-bindings.txt,

  the clocks are soc specific, the clock-names should be "iahb", "isfr"

-port@[X]: SoC specific port nodes with endpoint definitions as defined

   in Documentation/devicetree/bindings/media/video-interfaces.txt,

   please refer to the SoC specific binding document:

    * Documentation/devicetree/bindings/drm/imx/hdmi.txt

    * Documentation/devicetree/bindings/video/dw_hdmi-rockchip.txt



Optional properties

- reg-io-width: the width of the reg:1,4, default set to 1 if not present

- ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing

- clocks, clock-names: phandle to the HDMI CEC clock, name should be "cec"



Example:

	hdmi: hdmi@0120000 {

		compatible = "fsl,imx6q-hdmi";

		reg = <0x00120000 0x9000>;

		interrupts = <0 115 0x04>;

		gpr = <&gpr>;

		clocks = <&clks 123>, <&clks 124>;

		clock-names = "iahb", "isfr";

		ddc-i2c-bus = <&i2c2>;



		port@0 {

			reg = <0>;



			hdmi_mux_0: endpoint {

				remote-endpoint = <&ipu1_di0_hdmi>;

			};

		};



		port@1 {

			reg = <1>;



			hdmi_mux_1: endpoint {

				remote-endpoint = <&ipu1_di1_hdmi>;

			};

		};

	};

Documentation/devicetree/bindings/drm/msm/hdmi.txt

+2 −0
Original line number Diff line number Diff line
@@ -2,6 +2,8 @@ Qualcomm adreno/snapdragon hdmi output 


Required properties:

- compatible: one of the following

   * "qcom,hdmi-tx-8084"

   * "qcom,hdmi-tx-8074"

   * "qcom,hdmi-tx-8660"

   * "qcom,hdmi-tx-8960"

- reg: Physical base address and length of the controller's registers

Documentation/devicetree/bindings/gpu/st,stih4xx.txt

+29 −0
Original line number Diff line number Diff line
@@ -83,6 +83,22 @@ sti-hda: 
  - clock-names: names of the clocks listed in clocks property in the same

    order.



sti-dvo:

  Required properties:

  must be a child of sti-tvout

  - compatible: "st,stih<chip>-dvo"

  - reg: Physical base address of the IP registers and length of memory mapped region.

  - reg-names: names of the mapped memory regions listed in regs property in

    the same order.

  - clocks: from common clock binding: handle hardware IP needed clocks, the

    number of clocks may depend of the SoC type.

    See ../clocks/clock-bindings.txt for details.

  - clock-names: names of the clocks listed in clocks property in the same

    order.

  - pinctrl-0: pin control handle

  - pinctrl-name: names of the pin control to use

  - sti,panel: phandle of the panel connected to the DVO output



sti-hqvdp:

  must be a child of sti-display-subsystem

  Required properties:
@@ -198,6 +214,19 @@ Example: 
				clock-names	= "pix", "hddac";

				clocks          = <&clockgen_c_vcc CLK_S_PIX_HD>, <&clockgen_c_vcc CLK_S_HDDAC>;

			};



			sti-dvo@8d00400 {

				compatible	= "st,stih407-dvo";

				reg		= <0x8d00400 0x200>;

				reg-names	= "dvo-reg";

				clock-names	= "dvo_pix", "dvo",

						  "main_parent", "aux_parent";

				clocks		= <&clk_s_d2_flexgen CLK_PIX_DVO>, <&clk_s_d2_flexgen CLK_DVO>,

						  <&clk_s_d2_quadfs 0>, <&clk_s_d2_quadfs 1>;

				pinctrl-names	= "default";

				pinctrl-0	= <&pinctrl_dvo>;

				sti,panel	= <&panel_dvo>;

			};

		};



		sti-hqvdp@9c000000 {