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Commit 789b23bc authored by Nicolas Ferre's avatar Nicolas Ferre Committed by Russell King
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[ARM] 5572/1: at91: Support for at91sam9g45 series: core chip & board support 



Here are the at91 specific files dedicated to the at91sam9g45 series. They
mimic the traditional at91 way of managing chips & boards.

The first board that embeds at91sam9g45 chip is the AT91SAM9G45-EKES. In
the future, the main board for this 9g45 series will be the
AT91SAM9M10G45-EK (I choose this last name for the board file).

Simple drivers are enabled in _devices and board- files. Newer peripheral
support will be added in future patches.

Incuded peripherals support (for now):
- USART
- SPI
- Ethernet
- NAND flash
- LCD
- gpio/joystick/buttons
- leds and pwm

Signed-off-by: default avatarNicolas Ferre <nicolas.ferre@atmel.com>
Acked-by: default avatarAndrew Victor <linux@maxim.org.za>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent fddcc0ae

arch/arm/mach-at91/Kconfig

+24 −2
Original line number Diff line number Diff line
@@ -41,6 +41,12 @@ config ARCH_AT91SAM9G20 
	select GENERIC_TIME

	select GENERIC_CLOCKEVENTS



config ARCH_AT91SAM9G45

	bool "AT91SAM9G45"

	select CPU_ARM926T

	select GENERIC_TIME

	select GENERIC_CLOCKEVENTS



config ARCH_AT91CAP9

	bool "AT91CAP9"

	select CPU_ARM926T
@@ -280,6 +286,22 @@ endif 


# ----------------------------------------------------------



if ARCH_AT91SAM9G45



comment "AT91SAM9G45 Board Type"



config MACH_AT91SAM9G45EKES

	bool "Atmel AT91SAM9G45-EKES Evaluation Kit"

	depends on ARCH_AT91SAM9G45

	help

	  Select this if you are using Atmel's AT91SAM9G45-EKES Evaluation Kit.

	  "ES" at the end of the name means that this board is an

	  Engineering Sample.



endif



# ----------------------------------------------------------



if ARCH_AT91CAP9



comment "AT91CAP9 Board Type"
@@ -321,7 +343,7 @@ config MTD_AT91_DATAFLASH_CARD 


config MTD_NAND_ATMEL_BUSWIDTH_16

	bool "Enable 16-bit data bus interface to NAND flash"

	depends on (MACH_AT91SAM9260EK || MACH_AT91SAM9261EK || MACH_AT91SAM9263EK || MACH_AT91SAM9G20EK || MACH_AT91CAP9ADK)

	depends on (MACH_AT91SAM9260EK || MACH_AT91SAM9261EK || MACH_AT91SAM9263EK || MACH_AT91SAM9G20EK || MACH_AT91SAM9G45EKES || MACH_AT91CAP9ADK)

	help

	  On AT91SAM926x boards both types of NAND flash can be present

	  (8 and 16 bit data bus width).
@@ -383,7 +405,7 @@ config AT91_EARLY_USART2 


config AT91_EARLY_USART3

	bool "USART3"

	depends on (ARCH_AT91RM9200 || ARCH_AT91SAM9RL || ARCH_AT91SAM9260 || ARCH_AT91SAM9G20)

	depends on (ARCH_AT91RM9200 || ARCH_AT91SAM9RL || ARCH_AT91SAM9260 || ARCH_AT91SAM9G20 || ARCH_AT91SAM9G45)



config AT91_EARLY_USART4

	bool "USART4"

arch/arm/mach-at91/Makefile

+4 −0
Original line number Diff line number Diff line
@@ -16,6 +16,7 @@ obj-$(CONFIG_ARCH_AT91SAM9261) += at91sam9261.o at91sam926x_time.o at91sam9261_d 
obj-$(CONFIG_ARCH_AT91SAM9263)	+= at91sam9263.o at91sam926x_time.o at91sam9263_devices.o sam9_smc.o

obj-$(CONFIG_ARCH_AT91SAM9RL)	+= at91sam9rl.o at91sam926x_time.o at91sam9rl_devices.o sam9_smc.o

obj-$(CONFIG_ARCH_AT91SAM9G20)	+= at91sam9260.o at91sam926x_time.o at91sam9260_devices.o  sam9_smc.o

 obj-$(CONFIG_ARCH_AT91SAM9G45)	+= at91sam9g45.o at91sam926x_time.o at91sam9g45_devices.o sam9_smc.o

obj-$(CONFIG_ARCH_AT91CAP9)	+= at91cap9.o at91sam926x_time.o at91cap9_devices.o sam9_smc.o

obj-$(CONFIG_ARCH_AT91X40)	+= at91x40.o at91x40_time.o
@@ -55,6 +56,9 @@ obj-$(CONFIG_MACH_AT91SAM9RLEK) += board-sam9rlek.o 
# AT91SAM9G20 board-specific support

obj-$(CONFIG_MACH_AT91SAM9G20EK) += board-sam9g20ek.o



# AT91SAM9G45 board-specific support

obj-$(CONFIG_MACH_AT91SAM9G45EKES) += board-sam9m10g45ek.o



# AT91CAP9 board-specific support

obj-$(CONFIG_MACH_AT91CAP9ADK)	+= board-cap9adk.o

arch/arm/mach-at91/Makefile.boot

+4 −0
Original line number Diff line number Diff line
@@ -7,6 +7,10 @@ ifeq ($(CONFIG_ARCH_AT91CAP9),y) 
   zreladdr-y	:= 0x70008000

params_phys-y	:= 0x70000100

initrd_phys-y	:= 0x70410000

else ifeq ($(CONFIG_ARCH_AT91SAM9G45),y)

   zreladdr-y	:= 0x70008000

params_phys-y	:= 0x70000100

initrd_phys-y	:= 0x70410000

else

   zreladdr-y	:= 0x20008000

params_phys-y	:= 0x20000100

arch/arm/mach-at91/at91sam9g45.c

0 → 100644
+360 −0
Original line number Diff line number Diff line 
/*

 *  Chip-specific setup code for the AT91SAM9G45 family

 *

 *  Copyright (C) 2009 Atmel Corporation.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License as published by

 * the Free Software Foundation; either version 2 of the License, or

 * (at your option) any later version.

 *

 */



#include <linux/module.h>

#include <linux/pm.h>



#include <asm/irq.h>

#include <asm/mach/arch.h>

#include <asm/mach/map.h>

#include <mach/at91sam9g45.h>

#include <mach/at91_pmc.h>

#include <mach/at91_rstc.h>

#include <mach/at91_shdwc.h>



#include "generic.h"

#include "clock.h"



static struct map_desc at91sam9g45_io_desc[] __initdata = {

	{

		.virtual	= AT91_VA_BASE_SYS,

		.pfn		= __phys_to_pfn(AT91_BASE_SYS),

		.length		= SZ_16K,

		.type		= MT_DEVICE,

	}, {

		.virtual	= AT91_IO_VIRT_BASE - AT91SAM9G45_SRAM_SIZE,

		.pfn		= __phys_to_pfn(AT91SAM9G45_SRAM_BASE),

		.length		= AT91SAM9G45_SRAM_SIZE,

		.type		= MT_DEVICE,

	}

};



/* --------------------------------------------------------------------

 *  Clocks

 * -------------------------------------------------------------------- */



/*

 * The peripheral clocks.

 */

static struct clk pioA_clk = {

	.name		= "pioA_clk",

	.pmc_mask	= 1 << AT91SAM9G45_ID_PIOA,

	.type		= CLK_TYPE_PERIPHERAL,

};

static struct clk pioB_clk = {

	.name		= "pioB_clk",

	.pmc_mask	= 1 << AT91SAM9G45_ID_PIOB,

	.type		= CLK_TYPE_PERIPHERAL,

};

static struct clk pioC_clk = {

	.name		= "pioC_clk",

	.pmc_mask	= 1 << AT91SAM9G45_ID_PIOC,

	.type		= CLK_TYPE_PERIPHERAL,

};

static struct clk pioDE_clk = {

	.name		= "pioDE_clk",

	.pmc_mask	= 1 << AT91SAM9G45_ID_PIODE,

	.type		= CLK_TYPE_PERIPHERAL,

};

static struct clk usart0_clk = {

	.name		= "usart0_clk",

	.pmc_mask	= 1 << AT91SAM9G45_ID_US0,

	.type		= CLK_TYPE_PERIPHERAL,

};

static struct clk usart1_clk = {

	.name		= "usart1_clk",

	.pmc_mask	= 1 << AT91SAM9G45_ID_US1,

	.type		= CLK_TYPE_PERIPHERAL,

};

static struct clk usart2_clk = {

	.name		= "usart2_clk",

	.pmc_mask	= 1 << AT91SAM9G45_ID_US2,

	.type		= CLK_TYPE_PERIPHERAL,

};

static struct clk usart3_clk = {

	.name		= "usart3_clk",

	.pmc_mask	= 1 << AT91SAM9G45_ID_US3,

	.type		= CLK_TYPE_PERIPHERAL,

};

static struct clk mmc0_clk = {

	.name		= "mci0_clk",

	.pmc_mask	= 1 << AT91SAM9G45_ID_MCI0,

	.type		= CLK_TYPE_PERIPHERAL,

};

static struct clk twi0_clk = {

	.name		= "twi0_clk",

	.pmc_mask	= 1 << AT91SAM9G45_ID_TWI0,

	.type		= CLK_TYPE_PERIPHERAL,

};

static struct clk twi1_clk = {

	.name		= "twi1_clk",

	.pmc_mask	= 1 << AT91SAM9G45_ID_TWI1,

	.type		= CLK_TYPE_PERIPHERAL,

};

static struct clk spi0_clk = {

	.name		= "spi0_clk",

	.pmc_mask	= 1 << AT91SAM9G45_ID_SPI0,

	.type		= CLK_TYPE_PERIPHERAL,

};

static struct clk spi1_clk = {

	.name		= "spi1_clk",

	.pmc_mask	= 1 << AT91SAM9G45_ID_SPI1,

	.type		= CLK_TYPE_PERIPHERAL,

};

static struct clk ssc0_clk = {

	.name		= "ssc0_clk",

	.pmc_mask	= 1 << AT91SAM9G45_ID_SSC0,

	.type		= CLK_TYPE_PERIPHERAL,

};

static struct clk ssc1_clk = {

	.name		= "ssc1_clk",

	.pmc_mask	= 1 << AT91SAM9G45_ID_SSC1,

	.type		= CLK_TYPE_PERIPHERAL,

};

static struct clk tcb_clk = {

	.name		= "tcb_clk",

	.pmc_mask	= 1 << AT91SAM9G45_ID_TCB,

	.type		= CLK_TYPE_PERIPHERAL,

};

static struct clk pwm_clk = {

	.name		= "pwm_clk",

	.pmc_mask	= 1 << AT91SAM9G45_ID_PWMC,

	.type		= CLK_TYPE_PERIPHERAL,

};

static struct clk tsc_clk = {

	.name		= "tsc_clk",

	.pmc_mask	= 1 << AT91SAM9G45_ID_TSC,

	.type		= CLK_TYPE_PERIPHERAL,

};

static struct clk dma_clk = {

	.name		= "dma_clk",

	.pmc_mask	= 1 << AT91SAM9G45_ID_DMA,

	.type		= CLK_TYPE_PERIPHERAL,

};

static struct clk uhphs_clk = {

	.name		= "uhphs_clk",

	.pmc_mask	= 1 << AT91SAM9G45_ID_UHPHS,

	.type		= CLK_TYPE_PERIPHERAL,

};

static struct clk lcdc_clk = {

	.name		= "lcdc_clk",

	.pmc_mask	= 1 << AT91SAM9G45_ID_LCDC,

	.type		= CLK_TYPE_PERIPHERAL,

};

static struct clk ac97_clk = {

	.name		= "ac97_clk",

	.pmc_mask	= 1 << AT91SAM9G45_ID_AC97C,

	.type		= CLK_TYPE_PERIPHERAL,

};

static struct clk macb_clk = {

	.name		= "macb_clk",

	.pmc_mask	= 1 << AT91SAM9G45_ID_EMAC,

	.type		= CLK_TYPE_PERIPHERAL,

};

static struct clk isi_clk = {

	.name		= "isi_clk",

	.pmc_mask	= 1 << AT91SAM9G45_ID_ISI,

	.type		= CLK_TYPE_PERIPHERAL,

};

static struct clk udphs_clk = {

	.name		= "udphs_clk",

	.pmc_mask	= 1 << AT91SAM9G45_ID_UDPHS,

	.type		= CLK_TYPE_PERIPHERAL,

};

static struct clk mmc1_clk = {

	.name		= "mci1_clk",

	.pmc_mask	= 1 << AT91SAM9G45_ID_MCI1,

	.type		= CLK_TYPE_PERIPHERAL,

};



/* One additional fake clock for ohci */

static struct clk ohci_clk = {

	.name		= "ohci_clk",

	.pmc_mask	= 0,

	.type		= CLK_TYPE_PERIPHERAL,

	.parent		= &uhphs_clk,

};



static struct clk *periph_clocks[] __initdata = {

	&pioA_clk,

	&pioB_clk,

	&pioC_clk,

	&pioDE_clk,

	&usart0_clk,

	&usart1_clk,

	&usart2_clk,

	&usart3_clk,

	&mmc0_clk,

	&twi0_clk,

	&twi1_clk,

	&spi0_clk,

	&spi1_clk,

	&ssc0_clk,

	&ssc1_clk,

	&tcb_clk,

	&pwm_clk,

	&tsc_clk,

	&dma_clk,

	&uhphs_clk,

	&lcdc_clk,

	&ac97_clk,

	&macb_clk,

	&isi_clk,

	&udphs_clk,

	&mmc1_clk,

	// irq0

	&ohci_clk,

};



/*

 * The two programmable clocks.

 * You must configure pin multiplexing to bring these signals out.

 */

static struct clk pck0 = {

	.name		= "pck0",

	.pmc_mask	= AT91_PMC_PCK0,

	.type		= CLK_TYPE_PROGRAMMABLE,

	.id		= 0,

};

static struct clk pck1 = {

	.name		= "pck1",

	.pmc_mask	= AT91_PMC_PCK1,

	.type		= CLK_TYPE_PROGRAMMABLE,

	.id		= 1,

};



static void __init at91sam9g45_register_clocks(void)

{

	int i;



	for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)

		clk_register(periph_clocks[i]);



	clk_register(&pck0);

	clk_register(&pck1);

}



/* --------------------------------------------------------------------

 *  GPIO

 * -------------------------------------------------------------------- */



static struct at91_gpio_bank at91sam9g45_gpio[] = {

	{

		.id		= AT91SAM9G45_ID_PIOA,

		.offset		= AT91_PIOA,

		.clock		= &pioA_clk,

	}, {

		.id		= AT91SAM9G45_ID_PIOB,

		.offset		= AT91_PIOB,

		.clock		= &pioB_clk,

	}, {

		.id		= AT91SAM9G45_ID_PIOC,

		.offset		= AT91_PIOC,

		.clock		= &pioC_clk,

	}, {

		.id		= AT91SAM9G45_ID_PIODE,

		.offset		= AT91_PIOD,

		.clock		= &pioDE_clk,

	}, {

		.id		= AT91SAM9G45_ID_PIODE,

		.offset		= AT91_PIOE,

		.clock		= &pioDE_clk,

	}

};



static void at91sam9g45_reset(void)

{

	at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);

}



static void at91sam9g45_poweroff(void)

{

	at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);

}





/* --------------------------------------------------------------------

 *  AT91SAM9G45 processor initialization

 * -------------------------------------------------------------------- */



void __init at91sam9g45_initialize(unsigned long main_clock)

{

	/* Map peripherals */

	iotable_init(at91sam9g45_io_desc, ARRAY_SIZE(at91sam9g45_io_desc));



	at91_arch_reset = at91sam9g45_reset;

	pm_power_off = at91sam9g45_poweroff;

	at91_extern_irq = (1 << AT91SAM9G45_ID_IRQ0);



	/* Init clock subsystem */

	at91_clock_init(main_clock);



	/* Register the processor-specific clocks */

	at91sam9g45_register_clocks();



	/* Register GPIO subsystem */

	at91_gpio_init(at91sam9g45_gpio, 5);

}



/* --------------------------------------------------------------------

 *  Interrupt initialization

 * -------------------------------------------------------------------- */



/*

 * The default interrupt priority levels (0 = lowest, 7 = highest).

 */

static unsigned int at91sam9g45_default_irq_priority[NR_AIC_IRQS] __initdata = {

	7,	/* Advanced Interrupt Controller (FIQ) */

	7,	/* System Peripherals */

	1,	/* Parallel IO Controller A */

	1,	/* Parallel IO Controller B */

	1,	/* Parallel IO Controller C */

	1,	/* Parallel IO Controller D and E */

	0,

	5,	/* USART 0 */

	5,	/* USART 1 */

	5,	/* USART 2 */

	5,	/* USART 3 */

	0,	/* Multimedia Card Interface 0 */

	6,	/* Two-Wire Interface 0 */

	6,	/* Two-Wire Interface 1 */

	5,	/* Serial Peripheral Interface 0 */

	5,	/* Serial Peripheral Interface 1 */

	4,	/* Serial Synchronous Controller 0 */

	4,	/* Serial Synchronous Controller 1 */

	0,	/* Timer Counter 0, 1, 2, 3, 4 and 5 */

	0,	/* Pulse Width Modulation Controller */

	0,	/* Touch Screen Controller */

	0,	/* DMA Controller */

	2,	/* USB Host High Speed port */

	3,	/* LDC Controller */

	5,	/* AC97 Controller */

	3,	/* Ethernet */

	0,	/* Image Sensor Interface */

	2,	/* USB Device High speed port */

	0,

	0,	/* Multimedia Card Interface 1 */

	0,

	0,	/* Advanced Interrupt Controller (IRQ0) */

};



void __init at91sam9g45_init_interrupts(unsigned int priority[NR_AIC_IRQS])

{

	if (!priority)

		priority = at91sam9g45_default_irq_priority;



	/* Initialize the AIC interrupt controller */

	at91_aic_init(priority);



	/* Enable GPIO interrupts */

	at91_gpio_irq_setup();

}

arch/arm/mach-at91/at91sam9g45_devices.c

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