Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 78366f69 authored by Vladimir Kondratiev's avatar Vladimir Kondratiev Committed by Kalle Valo
Browse files

wil6210: add advanced interrupt moderation



Add advanced interrupt moderation support available since "Sparrow B0".
Legacy interrupt moderation used only one counter to moderate tx, rx,
and misc interrupts.
Advanced interrupt moderation bypasses misc, and handles separately tx
and rx interrupts. In addition it has two timers for each interrupt type.
Max burst duration timer which defines how long to postpone interrupt after
first event (receive event for rx and tx complete event for tx), and
interframe timeout which defines how to determine the end of the burst and
issue interrupt even if the first timer still pending.
Capabilities flags in wil_priv is set on initialization according to
HW. The rest of the code checks for advanced interrupt capability bit
in capabilities flags field.
Debugfs is split accordingly: "legacy" interrupt moderation remains
unchanged, new debugs files added for advanced interrupt moderation
support.
Module params are aligned to support advanced interrupt moderation
(tx & rx). When not available (for legacy interrupt moderation) will
use only rx configuration; Tx configuration will be ignored in this
case.

Signed-off-by: default avatarVladimir Kondratiev <qca_vkondrat@qca.qualcomm.com>
Signed-off-by: default avatarKalle Valo <kvalo@codeaurora.org>
parent 1aeda13b
Loading
Loading
Loading
Loading
+46 −3
Original line number Diff line number Diff line
@@ -390,24 +390,67 @@ static int wil6210_debugfs_create_pseudo_ISR(struct wil6210_priv *wil,
	return 0;
}

static const struct dbg_off itr_cnt_off[] = {
static const struct dbg_off lgc_itr_cnt_off[] = {
	{"TRSH", S_IRUGO | S_IWUSR, HOSTADDR(RGF_DMA_ITR_CNT_TRSH), doff_io32},
	{"DATA", S_IRUGO | S_IWUSR, HOSTADDR(RGF_DMA_ITR_CNT_DATA), doff_io32},
	{"CTL",  S_IRUGO | S_IWUSR, HOSTADDR(RGF_DMA_ITR_CNT_CRL), doff_io32},
	{},
};

static const struct dbg_off tx_itr_cnt_off[] = {
	{"TRSH", S_IRUGO | S_IWUSR, HOSTADDR(RGF_DMA_ITR_TX_CNT_TRSH),
	 doff_io32},
	{"DATA", S_IRUGO | S_IWUSR, HOSTADDR(RGF_DMA_ITR_TX_CNT_DATA),
	 doff_io32},
	{"CTL",  S_IRUGO | S_IWUSR, HOSTADDR(RGF_DMA_ITR_TX_CNT_CTL),
	 doff_io32},
	{"IDL_TRSH", S_IRUGO | S_IWUSR, HOSTADDR(RGF_DMA_ITR_TX_IDL_CNT_TRSH),
	 doff_io32},
	{"IDL_DATA", S_IRUGO | S_IWUSR, HOSTADDR(RGF_DMA_ITR_TX_IDL_CNT_DATA),
	 doff_io32},
	{"IDL_CTL",  S_IRUGO | S_IWUSR, HOSTADDR(RGF_DMA_ITR_TX_IDL_CNT_CTL),
	 doff_io32},
	{},
};

static const struct dbg_off rx_itr_cnt_off[] = {
	{"TRSH", S_IRUGO | S_IWUSR, HOSTADDR(RGF_DMA_ITR_RX_CNT_TRSH),
	 doff_io32},
	{"DATA", S_IRUGO | S_IWUSR, HOSTADDR(RGF_DMA_ITR_RX_CNT_DATA),
	 doff_io32},
	{"CTL",  S_IRUGO | S_IWUSR, HOSTADDR(RGF_DMA_ITR_RX_CNT_CTL),
	 doff_io32},
	{"IDL_TRSH", S_IRUGO | S_IWUSR, HOSTADDR(RGF_DMA_ITR_RX_IDL_CNT_TRSH),
	 doff_io32},
	{"IDL_DATA", S_IRUGO | S_IWUSR, HOSTADDR(RGF_DMA_ITR_RX_IDL_CNT_DATA),
	 doff_io32},
	{"IDL_CTL",  S_IRUGO | S_IWUSR, HOSTADDR(RGF_DMA_ITR_RX_IDL_CNT_CTL),
	 doff_io32},
	{},
};

static int wil6210_debugfs_create_ITR_CNT(struct wil6210_priv *wil,
					  struct dentry *parent)
{
	struct dentry *d = debugfs_create_dir("ITR_CNT", parent);
	struct dentry *d, *dtx, *drx;

	d = debugfs_create_dir("ITR_CNT", parent);
	if (IS_ERR_OR_NULL(d))
		return -ENODEV;

	dtx = debugfs_create_dir("TX", d);
	drx = debugfs_create_dir("RX", d);
	if (IS_ERR_OR_NULL(dtx) || IS_ERR_OR_NULL(drx))
		return -ENODEV;

	wil6210_debugfs_init_offset(wil, d, (void * __force)wil->csr,
				    itr_cnt_off);
				    lgc_itr_cnt_off);

	wil6210_debugfs_init_offset(wil, dtx, (void * __force)wil->csr,
				    tx_itr_cnt_off);

	wil6210_debugfs_init_offset(wil, drx, (void * __force)wil->csr,
				    rx_itr_cnt_off);
	return 0;
}

+34 −12
Original line number Diff line number Diff line
@@ -45,16 +45,35 @@ static int wil_ethtoolops_get_coalesce(struct net_device *ndev,
				       struct ethtool_coalesce *cp)
{
	struct wil6210_priv *wil = ndev_to_wil(ndev);
	u32 itr_en, itr_val = 0;
	u32 tx_itr_en, tx_itr_val = 0;
	u32 rx_itr_en, rx_itr_val = 0;

	wil_dbg_misc(wil, "%s()\n", __func__);

	itr_en = ioread32(wil->csr + HOSTADDR(RGF_DMA_ITR_CNT_CRL));
	if (itr_en & BIT_DMA_ITR_CNT_CRL_EN)
		itr_val = ioread32(wil->csr + HOSTADDR(RGF_DMA_ITR_CNT_TRSH));

	cp->rx_coalesce_usecs = itr_val;
	if (test_bit(hw_capability_advanced_itr_moderation,
		     wil->hw_capabilities)) {
		tx_itr_en = ioread32(wil->csr +
				     HOSTADDR(RGF_DMA_ITR_TX_CNT_CTL));
		if (tx_itr_en & BIT_DMA_ITR_TX_CNT_CTL_EN)
			tx_itr_val =
				ioread32(wil->csr +
					 HOSTADDR(RGF_DMA_ITR_TX_CNT_TRSH));

		rx_itr_en = ioread32(wil->csr +
				     HOSTADDR(RGF_DMA_ITR_RX_CNT_CTL));
		if (rx_itr_en & BIT_DMA_ITR_RX_CNT_CTL_EN)
			rx_itr_val =
				ioread32(wil->csr +
					 HOSTADDR(RGF_DMA_ITR_RX_CNT_TRSH));
	} else {
		rx_itr_en = ioread32(wil->csr + HOSTADDR(RGF_DMA_ITR_CNT_CRL));
		if (rx_itr_en & BIT_DMA_ITR_CNT_CRL_EN)
			rx_itr_val = ioread32(wil->csr +
					      HOSTADDR(RGF_DMA_ITR_CNT_TRSH));
	}

	cp->tx_coalesce_usecs = tx_itr_val;
	cp->rx_coalesce_usecs = rx_itr_val;
	return 0;
}

@@ -63,22 +82,25 @@ static int wil_ethtoolops_set_coalesce(struct net_device *ndev,
{
	struct wil6210_priv *wil = ndev_to_wil(ndev);

	wil_dbg_misc(wil, "%s(%d usec)\n", __func__, cp->rx_coalesce_usecs);
	wil_dbg_misc(wil, "%s(rx %d usec, tx %d usec)\n", __func__,
		     cp->rx_coalesce_usecs, cp->tx_coalesce_usecs);

	if (wil->wdev->iftype == NL80211_IFTYPE_MONITOR) {
		wil_dbg_misc(wil, "No IRQ coalescing in monitor mode\n");
		return -EINVAL;
	}

	/* only @rx_coalesce_usecs supported, ignore
	 * other parameters
	/* only @rx_coalesce_usecs and @tx_coalesce_usecs supported,
	 * ignore other parameters
	 */

	if (cp->rx_coalesce_usecs > WIL6210_ITR_TRSH_MAX)
	if (cp->rx_coalesce_usecs > WIL6210_ITR_TRSH_MAX ||
	    cp->tx_coalesce_usecs > WIL6210_ITR_TRSH_MAX)
		goto out_bad;

	wil->itr_trsh = cp->rx_coalesce_usecs;
	wil_set_itr_trsh(wil);
	wil->tx_max_burst_duration = cp->tx_coalesce_usecs;
	wil->rx_max_burst_duration = cp->rx_coalesce_usecs;
	wil_configure_interrupt_moderation(wil);

	return 0;

+79 −3
Original line number Diff line number Diff line
@@ -157,15 +157,91 @@ void wil_unmask_irq(struct wil6210_priv *wil)
	iowrite32(WIL_ICR_ICC_VALUE, wil->csr + HOSTADDR(RGF_DMA_EP_MISC_ICR) +
		  offsetof(struct RGF_ICR, ICC));

	/* interrupt moderation parameters */
	wil_set_itr_trsh(wil);

	wil6210_unmask_irq_pseudo(wil);
	wil6210_unmask_irq_tx(wil);
	wil6210_unmask_irq_rx(wil);
	wil6210_unmask_irq_misc(wil);
}

/* target write operation */
#define W(a, v) do { iowrite32(v, wil->csr + HOSTADDR(a)); wmb(); } while (0)

static
void wil_configure_interrupt_moderation_new(struct wil6210_priv *wil)
{
	/* Disable and clear tx counter before (re)configuration */
	W(RGF_DMA_ITR_TX_CNT_CTL, BIT_DMA_ITR_TX_CNT_CTL_CLR);
	W(RGF_DMA_ITR_TX_CNT_TRSH, wil->tx_max_burst_duration);
	wil_info(wil, "set ITR_TX_CNT_TRSH = %d usec\n",
		 wil->tx_max_burst_duration);
	/* Configure TX max burst duration timer to use usec units */
	W(RGF_DMA_ITR_TX_CNT_CTL,
	  BIT_DMA_ITR_TX_CNT_CTL_EN | BIT_DMA_ITR_TX_CNT_CTL_EXT_TIC_SEL);

	/* Disable and clear tx idle counter before (re)configuration */
	W(RGF_DMA_ITR_TX_IDL_CNT_CTL, BIT_DMA_ITR_TX_IDL_CNT_CTL_CLR);
	W(RGF_DMA_ITR_TX_IDL_CNT_TRSH, wil->tx_interframe_timeout);
	wil_info(wil, "set ITR_TX_IDL_CNT_TRSH = %d usec\n",
		 wil->tx_interframe_timeout);
	/* Configure TX max burst duration timer to use usec units */
	W(RGF_DMA_ITR_TX_IDL_CNT_CTL, BIT_DMA_ITR_TX_IDL_CNT_CTL_EN |
				      BIT_DMA_ITR_TX_IDL_CNT_CTL_EXT_TIC_SEL);

	/* Disable and clear rx counter before (re)configuration */
	W(RGF_DMA_ITR_RX_CNT_CTL, BIT_DMA_ITR_RX_CNT_CTL_CLR);
	W(RGF_DMA_ITR_RX_CNT_TRSH, wil->rx_max_burst_duration);
	wil_info(wil, "set ITR_RX_CNT_TRSH = %d usec\n",
		 wil->rx_max_burst_duration);
	/* Configure TX max burst duration timer to use usec units */
	W(RGF_DMA_ITR_RX_CNT_CTL,
	  BIT_DMA_ITR_RX_CNT_CTL_EN | BIT_DMA_ITR_RX_CNT_CTL_EXT_TIC_SEL);

	/* Disable and clear rx idle counter before (re)configuration */
	W(RGF_DMA_ITR_RX_IDL_CNT_CTL, BIT_DMA_ITR_RX_IDL_CNT_CTL_CLR);
	W(RGF_DMA_ITR_RX_IDL_CNT_TRSH, wil->rx_interframe_timeout);
	wil_info(wil, "set ITR_RX_IDL_CNT_TRSH = %d usec\n",
		 wil->rx_interframe_timeout);
	/* Configure TX max burst duration timer to use usec units */
	W(RGF_DMA_ITR_RX_IDL_CNT_CTL, BIT_DMA_ITR_RX_IDL_CNT_CTL_EN |
				      BIT_DMA_ITR_RX_IDL_CNT_CTL_EXT_TIC_SEL);
}

static
void wil_configure_interrupt_moderation_lgc(struct wil6210_priv *wil)
{
	/* disable, use usec resolution */
	W(RGF_DMA_ITR_CNT_CRL, BIT_DMA_ITR_CNT_CRL_CLR);

	wil_info(wil, "set ITR_TRSH = %d usec\n", wil->rx_max_burst_duration);
	W(RGF_DMA_ITR_CNT_TRSH, wil->rx_max_burst_duration);
	/* start it */
	W(RGF_DMA_ITR_CNT_CRL,
	  BIT_DMA_ITR_CNT_CRL_EN | BIT_DMA_ITR_CNT_CRL_EXT_TICK);
}

#undef W

void wil_configure_interrupt_moderation(struct wil6210_priv *wil)
{
	wil_dbg_irq(wil, "%s()\n", __func__);

	/* disable interrupt moderation for monitor
	 * to get better timestamp precision
	 */
	if (wil->wdev->iftype == NL80211_IFTYPE_MONITOR)
		return;

	if (test_bit(hw_capability_advanced_itr_moderation,
		     wil->hw_capabilities))
		wil_configure_interrupt_moderation_new(wil);
	else {
		/* Advanced interrupt moderation is not available before
		 * Sparrow v2. Will use legacy interrupt moderation
		 */
		wil_configure_interrupt_moderation_lgc(wil);
	}
}

static irqreturn_t wil6210_irq_rx(int irq, void *cookie)
{
	struct wil6210_priv *wil = cookie;
+32 −24
Original line number Diff line number Diff line
@@ -33,10 +33,34 @@ static bool no_fw_load = true;
module_param(no_fw_load, bool, S_IRUGO | S_IWUSR);
MODULE_PARM_DESC(no_fw_load, " do not download FW, use one in on-card flash.");

static unsigned int itr_trsh = WIL6210_ITR_TRSH_DEFAULT;
static unsigned int tx_interframe_timeout =
		WIL6210_ITR_TX_INTERFRAME_TIMEOUT_DEFAULT;

module_param(tx_interframe_timeout, uint, S_IRUGO);
MODULE_PARM_DESC(tx_interframe_timeout,
		 " Interrupt moderation TX interframe timeout, usecs.");

static unsigned int rx_interframe_timeout =
		WIL6210_ITR_RX_INTERFRAME_TIMEOUT_DEFAULT;

module_param(rx_interframe_timeout, uint, S_IRUGO);
MODULE_PARM_DESC(rx_interframe_timeout,
		 " Interrupt moderation RX interframe timeout, usecs.");

static unsigned int tx_max_burst_duration =
		WIL6210_ITR_TX_MAX_BURST_DURATION_DEFAULT;

module_param(tx_max_burst_duration, uint, S_IRUGO);
MODULE_PARM_DESC(tx_max_burst_duration,
		 " Interrupt moderation TX max burst duration, usecs.");

static unsigned int rx_max_burst_duration =
		WIL6210_ITR_RX_MAX_BURST_DURATION_DEFAULT;

module_param(rx_max_burst_duration, uint, S_IRUGO);
MODULE_PARM_DESC(rx_max_burst_duration,
		 " Interrupt moderation RX max burst duration, usecs.");

module_param(itr_trsh, uint, S_IRUGO);
MODULE_PARM_DESC(itr_trsh, " Interrupt moderation threshold, usecs.");

/* We allow allocation of more than 1 page buffers to support large packets.
 * It is suboptimal behavior performance wise in case MTU above page size.
@@ -427,7 +451,10 @@ int wil_priv_init(struct wil6210_priv *wil)
		goto out_wmi_wq;

	wil->last_fw_recovery = jiffies;
	wil->itr_trsh = itr_trsh;
	wil->tx_interframe_timeout = tx_interframe_timeout;
	wil->rx_interframe_timeout = rx_interframe_timeout;
	wil->tx_max_burst_duration = tx_max_burst_duration;
	wil->rx_max_burst_duration = rx_max_burst_duration;

	return 0;

@@ -585,26 +612,6 @@ static int wil_target_reset(struct wil6210_priv *wil)
	return 0;
}

/**
 * wil_set_itr_trsh: - apply interrupt coalescing params
 */
void wil_set_itr_trsh(struct wil6210_priv *wil)
{
	/* disable, use usec resolution */
	W(RGF_DMA_ITR_CNT_CRL, BIT_DMA_ITR_CNT_CRL_EXT_TICK);

	/* disable interrupt moderation for monitor
	 * to get better timestamp precision
	 */
	if (wil->wdev->iftype == NL80211_IFTYPE_MONITOR)
		return;

	wil_info(wil, "set ITR_TRSH = %d usec\n", wil->itr_trsh);
	W(RGF_DMA_ITR_CNT_TRSH, wil->itr_trsh);
	W(RGF_DMA_ITR_CNT_CRL, BIT_DMA_ITR_CNT_CRL_EN |
	  BIT_DMA_ITR_CNT_CRL_EXT_TICK); /* start it */
}

#undef R
#undef W
#undef S
@@ -708,6 +715,7 @@ int wil_reset(struct wil6210_priv *wil)
	reinit_completion(&wil->wmi_ready);
	reinit_completion(&wil->wmi_call);

	wil_configure_interrupt_moderation(wil);
	wil_unmask_irq(wil);

	/* we just started MAC, wait for FW ready */
+4 −0
Original line number Diff line number Diff line
@@ -65,6 +65,10 @@ void wil_set_capabilities(struct wil6210_priv *wil)

	if (wil->hw_version >= HW_VER_SPARROW_A0)
		set_bit(hw_capability_reset_v2, wil->hw_capabilities);

	if (wil->hw_version >= HW_VER_SPARROW_B0)
		set_bit(hw_capability_advanced_itr_moderation,
			wil->hw_capabilities);
}

void wil_disable_irq(struct wil6210_priv *wil)
Loading