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Commit 780f0aeb authored by arun.siluvery@linux.intel.com's avatar arun.siluvery@linux.intel.com Committed by Tvrtko Ursulin
Browse files

drm/i915/bxt: Add WaDisablePooledEuLoadBalancingFix 



This is a WA affecting pooled eu which is a bxt specific feature.

Reviewed-by: default avatarMika Kuoppala <mika.kuoppala@intel.com>
Cc: Winiarski, Michal <michal.winiarski@intel.com>
Cc: Zou, Nanhai <nanhai.zou@intel.com>
Cc: Yang, Rong R <rong.r.yang@intel.com>
Cc: Jeff McGee <jeff.mcgee@intel.com>
Signed-off-by: default avatarArun Siluvery <arun.siluvery@linux.intel.com>
Signed-off-by: default avatarTvrtko Ursulin <tvrtko.ursulin@intel.com>
parent e015dd69

drivers/gpu/drm/i915/i915_reg.h

+1 −0
Original line number Diff line number Diff line
@@ -6106,6 +6106,7 @@ enum skl_disp_power_wells { 


#define FF_SLICE_CS_CHICKEN2			_MMIO(0x20e4)

#define  GEN9_TSG_BARRIER_ACK_DISABLE		(1<<8)

#define  GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE  (1<<10)



#define GEN9_CS_DEBUG_MODE1		_MMIO(0x20ec)

#define GEN9_CTX_PREEMPT_REG		_MMIO(0x2248)

drivers/gpu/drm/i915/intel_ringbuffer.c

+6 −0
Original line number Diff line number Diff line
@@ -1160,6 +1160,12 @@ static int bxt_init_workarounds(struct intel_engine_cs *engine) 
	WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,

			  STALL_DOP_GATING_DISABLE);



	/* WaDisablePooledEuLoadBalancingFix:bxt */

	if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER)) {

		WA_SET_BIT_MASKED(FF_SLICE_CS_CHICKEN2,

				  GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE);

	}



	/* WaDisableSbeCacheDispatchPortSharing:bxt */

	if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0)) {

		WA_SET_BIT_MASKED(