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Commit 77321959 authored by Antoine Tenart's avatar Antoine Tenart Committed by David S. Miller
Browse files

net: mvpp2: initialize the XLG MAC when using a port 



This adds a routine to initialize the XLG MAC at the port level when
using a port and the XAUI/10GKR interface mode. This wasn't done until
this commit, and the mvpp2 driver was relying on the bootloader/firmware
initialization. This doesn't mean everything is configured in the mvpp2
driver now, but it helps reducing the gap.

Signed-off-by: default avatarAntoine Tenart <antoine.tenart@free-electrons.com>
Tested-by: default avatarMarcin Wojtas <mw@semihalf.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 3919357f

drivers/net/ethernet/marvell/mvpp2.c

+25 −0
Original line number Diff line number Diff line
@@ -361,6 +361,7 @@ 
#define MVPP22_XLG_CTRL0_REG			0x100

#define     MVPP22_XLG_CTRL0_PORT_EN		BIT(0)

#define     MVPP22_XLG_CTRL0_MAC_RESET_DIS	BIT(1)

#define     MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN	BIT(7)

#define     MVPP22_XLG_CTRL0_MIB_CNT_DIS	BIT(14)



#define MVPP22_XLG_CTRL3_REG			0x11c
@@ -368,6 +369,11 @@ 
#define     MVPP22_XLG_CTRL3_MACMODESELECT_GMAC	(0 << 13)

#define     MVPP22_XLG_CTRL3_MACMODESELECT_10G	(1 << 13)



#define MVPP22_XLG_CTRL4_REG			0x184

#define     MVPP22_XLG_CTRL4_FWD_FC		BIT(5)

#define     MVPP22_XLG_CTRL4_FWD_PFC		BIT(6)

#define     MVPP22_XLG_CTRL4_MACMODSELECT_GMAC	BIT(12)



/* SMI registers. PPv2.2 only, relative to priv->iface_base. */

#define MVPP22_SMI_MISC_CFG_REG			0x1204

#define     MVPP22_SMI_POLLING_EN		BIT(10)
@@ -4337,6 +4343,23 @@ static void mvpp2_port_mii_gmac_configure(struct mvpp2_port *port) 
	writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);

}



static void mvpp2_port_mii_xlg_configure(struct mvpp2_port *port)

{

	u32 val;



	if (port->gop_id != 0)

		return;



	val = readl(port->base + MVPP22_XLG_CTRL0_REG);

	val |= MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN;

	writel(val, port->base + MVPP22_XLG_CTRL0_REG);



	val = readl(port->base + MVPP22_XLG_CTRL4_REG);

	val &= ~MVPP22_XLG_CTRL4_MACMODSELECT_GMAC;

	val |= MVPP22_XLG_CTRL4_FWD_FC | MVPP22_XLG_CTRL4_FWD_PFC;

	writel(val, port->base + MVPP22_XLG_CTRL4_REG);

}



static void mvpp22_port_mii_set(struct mvpp2_port *port)

{

	u32 val;
@@ -4367,6 +4390,8 @@ static void mvpp2_port_mii_set(struct mvpp2_port *port) 
	    port->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID ||

	    port->phy_interface == PHY_INTERFACE_MODE_SGMII)

		mvpp2_port_mii_gmac_configure(port);

	else if (port->phy_interface == PHY_INTERFACE_MODE_10GKR)

		mvpp2_port_mii_xlg_configure(port);

}



static void mvpp2_port_fc_adv_enable(struct mvpp2_port *port)