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Commit 771decb0 authored by Sagar Arun Kamble's avatar Sagar Arun Kamble Committed by Chris Wilson
Browse files

drm/i915: Rename intel_enable_rc6 to intel_rc6_enabled 



This function gives the status of RC6, whether disabled or if
enabled then which state. intel_enable_rc6 will be used for
enabling RC6 in the next patch.

v2: Rebase.

v3: Rebase.

Signed-off-by: default avatarSagar Arun Kamble <sagar.a.kamble@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Reviewed-by: Radoslaw Szwichtenberg <radoslaw.szwichtenberg@intel.com> #1
Reviewed-by: Ewelina Musial <ewelina.musial@intel.com> #1
Reviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/1507360055-19948-10-git-send-email-sagar.a.kamble@intel.com


Acked-by: default avatarImre Deak <imre.deak@intel.com>
Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20171010213010.7415-9-chris@chris-wilson.co.uk
parent 562d9bae

drivers/gpu/drm/i915/i915_drv.c

+1 −1
Original line number Diff line number Diff line
@@ -2502,7 +2502,7 @@ static int intel_runtime_suspend(struct device *kdev) 
	struct drm_i915_private *dev_priv = to_i915(dev);

	int ret;



	if (WARN_ON_ONCE(!(dev_priv->gt_pm.rps.enabled && intel_enable_rc6())))

	if (WARN_ON_ONCE(!(dev_priv->gt_pm.rps.enabled && intel_rc6_enabled())))

		return -ENODEV;



	if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))

drivers/gpu/drm/i915/i915_sysfs.c

+1 −1
Original line number Diff line number Diff line
@@ -49,7 +49,7 @@ static u32 calc_residency(struct drm_i915_private *dev_priv, 
static ssize_t

show_rc6_mask(struct device *kdev, struct device_attribute *attr, char *buf)

{

	return snprintf(buf, PAGE_SIZE, "%x\n", intel_enable_rc6());

	return snprintf(buf, PAGE_SIZE, "%x\n", intel_rc6_enabled());

}



static ssize_t

drivers/gpu/drm/i915/intel_drv.h

+1 −1
Original line number Diff line number Diff line
@@ -1903,7 +1903,7 @@ int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc, 
				  struct intel_crtc_state *cstate);

void intel_init_ipc(struct drm_i915_private *dev_priv);

void intel_enable_ipc(struct drm_i915_private *dev_priv);

static inline int intel_enable_rc6(void)

static inline int intel_rc6_enabled(void)

{

	return i915_modparams.enable_rc6;

}

drivers/gpu/drm/i915/intel_guc.c

+2 −1
Original line number Diff line number Diff line
@@ -137,7 +137,8 @@ int intel_guc_sample_forcewake(struct intel_guc *guc) 


	action[0] = INTEL_GUC_ACTION_SAMPLE_FORCEWAKE;

	/* WaRsDisableCoarsePowerGating:skl,bxt */

	if (!intel_enable_rc6() || NEEDS_WaRsDisableCoarsePowerGating(dev_priv))

	if (!intel_rc6_enabled() ||

	    NEEDS_WaRsDisableCoarsePowerGating(dev_priv))

		action[1] = 0;

	else

		/* bit 0 and 1 are for Render and Media domain separately */

drivers/gpu/drm/i915/intel_pm.c

+6 −6
Original line number Diff line number Diff line
@@ -6625,7 +6625,7 @@ static void gen9_enable_rc6(struct drm_i915_private *dev_priv) 
	I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);



	/* 3a: Enable RC6 */

	if (intel_enable_rc6() & INTEL_RC6_ENABLE)

	if (intel_rc6_enabled() & INTEL_RC6_ENABLE)

		rc6_mask = GEN6_RC_CTL_RC6_ENABLE;

	DRM_INFO("RC6 %s\n", onoff(rc6_mask & GEN6_RC_CTL_RC6_ENABLE));

	I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
@@ -6671,7 +6671,7 @@ static void gen8_enable_rc6(struct drm_i915_private *dev_priv) 
	I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */



	/* 3: Enable RC6 */

	if (intel_enable_rc6() & INTEL_RC6_ENABLE)

	if (intel_rc6_enabled() & INTEL_RC6_ENABLE)

		rc6_mask = GEN6_RC_CTL_RC6_ENABLE;

	intel_print_rc6_info(dev_priv, rc6_mask);
@@ -6766,7 +6766,7 @@ static void gen6_enable_rc6(struct drm_i915_private *dev_priv) 
	I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */



	/* Check if we are enabling RC6 */

	rc6_mode = intel_enable_rc6();

	rc6_mode = intel_rc6_enabled();

	if (rc6_mode & INTEL_RC6_ENABLE)

		rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
@@ -7268,7 +7268,7 @@ static void cherryview_enable_rc6(struct drm_i915_private *dev_priv) 
	pcbr = I915_READ(VLV_PCBR);



	/* 3: Enable RC6 */

	if ((intel_enable_rc6() & INTEL_RC6_ENABLE) &&

	if ((intel_rc6_enabled() & INTEL_RC6_ENABLE) &&

	    (pcbr >> VLV_PCBR_ADDR_SHIFT))

		rc6_mode = GEN7_RC_CTL_TO_MODE;
@@ -7360,7 +7360,7 @@ static void valleyview_enable_rc6(struct drm_i915_private *dev_priv) 
				      VLV_MEDIA_RC6_COUNT_EN |

				      VLV_RENDER_RC6_COUNT_EN));



	if (intel_enable_rc6() & INTEL_RC6_ENABLE)

	if (intel_rc6_enabled() & INTEL_RC6_ENABLE)

		rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;



	intel_print_rc6_info(dev_priv, rc6_mode);
@@ -9437,7 +9437,7 @@ u64 intel_rc6_residency_us(struct drm_i915_private *dev_priv, 
{

	u64 time_hw, units, div;



	if (!intel_enable_rc6())

	if (!intel_rc6_enabled())

		return 0;



	intel_runtime_pm_get(dev_priv);