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Commit 76f80322 authored by Chen-Yu Tsai's avatar Chen-Yu Tsai
Browse files

ARM: dts: sun8i: r40: Add device node and RGMII pinmux node for GMAC 



The R40 SoC has a GMAC (gigabit capable Ethernet controller). Add a
device node for it. The only publicly available board for this SoC
uses an RGMII PHY. Add a pinmux node for it as well.

Since this SoC also has an old 10/100 Mbps EMAC, which also has an
MDIO bus controller, the MDIO bus for the GMAC is labeled "gmac_mdio".

Acked-by: default avatarMaxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: default avatarChen-Yu Tsai <wens@csie.org>
parent 02b301f5

arch/arm/boot/dts/sun8i-r40.dtsi

+34 −0
Original line number Diff line number Diff line
@@ -265,6 +265,19 @@ 
			#interrupt-cells = <3>;

			#gpio-cells = <3>;



			gmac_rgmii_pins: gmac-rgmii-pins {

				pins = "PA0", "PA1", "PA2", "PA3",

				       "PA4", "PA5", "PA6", "PA7",

				       "PA8", "PA10", "PA11", "PA12",

				       "PA13", "PA15", "PA16";

				function = "gmac";

				/*

				 * data lines in RGMII mode use DDR mode

				 * and need a higher signal drive strength

				 */

				drive-strength = <40>;

			};



			i2c0_pins: i2c0-pins {

				pins = "PB0", "PB1";

				function = "i2c0";
@@ -451,6 +464,27 @@ 
			#size-cells = <0>;

		};



		gmac: ethernet@1c50000 {

			compatible = "allwinner,sun8i-r40-gmac";

			syscon = <&ccu>;

			reg = <0x01c50000 0x10000>;

			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "macirq";

			resets = <&ccu RST_BUS_GMAC>;

			reset-names = "stmmaceth";

			clocks = <&ccu CLK_BUS_GMAC>;

			clock-names = "stmmaceth";

			#address-cells = <1>;

			#size-cells = <0>;

			status = "disabled";



			gmac_mdio: mdio {

				compatible = "snps,dwmac-mdio";

				#address-cells = <1>;

				#size-cells = <0>;

			};

		};



		gic: interrupt-controller@1c81000 {

			compatible = "arm,gic-400";

			reg = <0x01c81000 0x1000>,