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Commit 76c9dd9d authored by David Lechner's avatar David Lechner Committed by Michael Turquette
Browse files

clk: davinci: pll: allow dev == NULL 



This modifies the TI Davinci PLL clock driver to allow for the case
when dev == NULL. On some (most) SoCs that use this driver, the PLL
clock needs to be registered during early boot because it is used
for clocksource/clkevent and there will be no platform device available.

Signed-off-by: default avatarDavid Lechner <david@lechnology.com>
Reviewed-by: default avatarSekhar Nori <nsekhar@ti.com>
Signed-off-by: default avatarMichael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/20180525181150.17873-7-david@lechnology.com
parent 9c39fc1f

drivers/clk/davinci/pll-da830.c

+3 −2
Original line number Diff line number Diff line
@@ -6,6 +6,7 @@ 
 */



#include <linux/clkdev.h>

#include <linux/clk/davinci.h>

#include <linux/bitops.h>

#include <linux/init.h>

#include <linux/types.h>
@@ -36,11 +37,11 @@ SYSCLK(5, pll0_sysclk5, pll0_pllen, 5, 0); 
SYSCLK(6, pll0_sysclk6, pll0_pllen, 5, SYSCLK_FIXED_DIV);

SYSCLK(7, pll0_sysclk7, pll0_pllen, 5, 0);



int da830_pll_init(struct device *dev, void __iomem *base)

int da830_pll_init(struct device *dev, void __iomem *base, struct regmap *cfgchip)

{

	struct clk *clk;



	davinci_pll_clk_register(dev, &da830_pll_info, "ref_clk", base);

	davinci_pll_clk_register(dev, &da830_pll_info, "ref_clk", base, cfgchip);



	clk = davinci_pll_sysclk_register(dev, &pll0_sysclk2, base);

	clk_register_clkdev(clk, "pll0_sysclk2", "da830-psc0");

drivers/clk/davinci/pll-da850.c

+12 −10
Original line number Diff line number Diff line
@@ -7,7 +7,9 @@ 


#include <linux/bitops.h>

#include <linux/clk-provider.h>

#include <linux/clk/davinci.h>

#include <linux/clkdev.h>

#include <linux/device.h>

#include <linux/init.h>

#include <linux/kernel.h>

#include <linux/mfd/da8xx-cfgchip.h>
@@ -81,11 +83,11 @@ static const struct davinci_pll_obsclk_info da850_pll0_obsclk_info = { 
	.ocsrc_mask = GENMASK(4, 0),

};



int da850_pll0_init(struct device *dev, void __iomem *base)

int da850_pll0_init(struct device *dev, void __iomem *base, struct regmap *cfgchip)

{

	struct clk *clk;



	davinci_pll_clk_register(dev, &da850_pll0_info, "ref_clk", base);

	davinci_pll_clk_register(dev, &da850_pll0_info, "ref_clk", base, cfgchip);



	clk = davinci_pll_sysclk_register(dev, &pll0_sysclk1, base);

	clk_register_clkdev(clk, "pll0_sysclk1", "da850-psc0");
@@ -134,11 +136,11 @@ static const struct davinci_pll_sysclk_info *da850_pll0_sysclk_info[] = { 
	NULL

};



int of_da850_pll0_init(struct device *dev, void __iomem *base)

int of_da850_pll0_init(struct device *dev, void __iomem *base, struct regmap *cfgchip)

{

	return of_davinci_pll_init(dev, &da850_pll0_info,

	return of_davinci_pll_init(dev, dev->of_node, &da850_pll0_info,

				   &da850_pll0_obsclk_info,

				   da850_pll0_sysclk_info, 7, base);

				   da850_pll0_sysclk_info, 7, base, cfgchip);

}



static const struct davinci_pll_clk_info da850_pll1_info = {
@@ -179,11 +181,11 @@ static const struct davinci_pll_obsclk_info da850_pll1_obsclk_info = { 
	.ocsrc_mask = GENMASK(4, 0),

};



int da850_pll1_init(struct device *dev, void __iomem *base)

int da850_pll1_init(struct device *dev, void __iomem *base, struct regmap *cfgchip)

{

	struct clk *clk;



	davinci_pll_clk_register(dev, &da850_pll1_info, "oscin", base);

	davinci_pll_clk_register(dev, &da850_pll1_info, "oscin", base, cfgchip);



	davinci_pll_sysclk_register(dev, &pll1_sysclk1, base);
@@ -204,9 +206,9 @@ static const struct davinci_pll_sysclk_info *da850_pll1_sysclk_info[] = { 
	NULL

};



int of_da850_pll1_init(struct device *dev, void __iomem *base)

int of_da850_pll1_init(struct device *dev, void __iomem *base, struct regmap *cfgchip)

{

	return of_davinci_pll_init(dev, &da850_pll1_info,

	return of_davinci_pll_init(dev, dev->of_node, &da850_pll1_info,

				   &da850_pll1_obsclk_info,

				   da850_pll1_sysclk_info, 3, base);

				   da850_pll1_sysclk_info, 3, base, cfgchip);

}

drivers/clk/davinci/pll-dm355.c

+5 −4
Original line number Diff line number Diff line
@@ -6,6 +6,7 @@ 
 */



#include <linux/bitops.h>

#include <linux/clk/davinci.h>

#include <linux/clkdev.h>

#include <linux/init.h>

#include <linux/types.h>
@@ -27,11 +28,11 @@ SYSCLK(2, pll1_sysclk2, pll1_pllen, 5, SYSCLK_FIXED_DIV | SYSCLK_ALWAYS_ENABLED) 
SYSCLK(3, pll1_sysclk3, pll1_pllen, 5, SYSCLK_ALWAYS_ENABLED);

SYSCLK(4, pll1_sysclk4, pll1_pllen, 5, SYSCLK_ALWAYS_ENABLED);



int dm355_pll1_init(struct device *dev, void __iomem *base)

int dm355_pll1_init(struct device *dev, void __iomem *base, struct regmap *cfgchip)

{

	struct clk *clk;



	davinci_pll_clk_register(dev, &dm355_pll1_info, "ref_clk", base);

	davinci_pll_clk_register(dev, &dm355_pll1_info, "ref_clk", base, cfgchip);



	clk = davinci_pll_sysclk_register(dev, &pll1_sysclk1, base);

	clk_register_clkdev(clk, "pll1_sysclk1", "dm355-psc");
@@ -64,9 +65,9 @@ static const struct davinci_pll_clk_info dm355_pll2_info = { 


SYSCLK(1, pll2_sysclk1, pll2_pllen, 5, SYSCLK_FIXED_DIV | SYSCLK_ALWAYS_ENABLED);



int dm355_pll2_init(struct device *dev, void __iomem *base)

int dm355_pll2_init(struct device *dev, void __iomem *base, struct regmap *cfgchip)

{

	davinci_pll_clk_register(dev, &dm355_pll2_info, "oscin", base);

	davinci_pll_clk_register(dev, &dm355_pll2_info, "oscin", base, cfgchip);



	davinci_pll_sysclk_register(dev, &pll2_sysclk1, base);

drivers/clk/davinci/pll-dm365.c

+5 −4
Original line number Diff line number Diff line
@@ -7,6 +7,7 @@ 


#include <linux/bitops.h>

#include <linux/clkdev.h>

#include <linux/clk/davinci.h>

#include <linux/init.h>

#include <linux/kernel.h>

#include <linux/types.h>
@@ -56,11 +57,11 @@ static const struct davinci_pll_obsclk_info dm365_pll1_obsclk_info = { 
	.ocsrc_mask = BIT(4),

};



int dm365_pll1_init(struct device *dev, void __iomem *base)

int dm365_pll1_init(struct device *dev, void __iomem *base, struct regmap *cfgchip)

{

	struct clk *clk;



	davinci_pll_clk_register(dev, &dm365_pll1_info, "ref_clk", base);

	davinci_pll_clk_register(dev, &dm365_pll1_info, "ref_clk", base, cfgchip);



	clk = davinci_pll_sysclk_register(dev, &pll1_sysclk1, base);

	clk_register_clkdev(clk, "pll1_sysclk1", "dm365-psc");
@@ -119,11 +120,11 @@ static const struct davinci_pll_obsclk_info dm365_pll2_obsclk_info = { 
	.ocsrc_mask = BIT(4),

};



int dm365_pll2_init(struct device *dev, void __iomem *base)

int dm365_pll2_init(struct device *dev, void __iomem *base, struct regmap *cfgchip)

{

	struct clk *clk;



	davinci_pll_clk_register(dev, &dm365_pll2_info, "oscin", base);

	davinci_pll_clk_register(dev, &dm365_pll2_info, "oscin", base, cfgchip);



	davinci_pll_sysclk_register(dev, &pll2_sysclk1, base);

drivers/clk/davinci/pll-dm644x.c

+5 −4
Original line number Diff line number Diff line
@@ -6,6 +6,7 @@ 
 */



#include <linux/bitops.h>

#include <linux/clk/davinci.h>

#include <linux/clkdev.h>

#include <linux/init.h>

#include <linux/types.h>
@@ -27,11 +28,11 @@ SYSCLK(2, pll1_sysclk2, pll1_pllen, 4, SYSCLK_FIXED_DIV); 
SYSCLK(3, pll1_sysclk3, pll1_pllen, 4, SYSCLK_FIXED_DIV);

SYSCLK(5, pll1_sysclk5, pll1_pllen, 4, SYSCLK_FIXED_DIV);



int dm644x_pll1_init(struct device *dev, void __iomem *base)

int dm644x_pll1_init(struct device *dev, void __iomem *base, struct regmap *cfgchip)

{

	struct clk *clk;



	davinci_pll_clk_register(dev, &dm644x_pll1_info, "ref_clk", base);

	davinci_pll_clk_register(dev, &dm644x_pll1_info, "ref_clk", base, cfgchip);



	clk = davinci_pll_sysclk_register(dev, &pll1_sysclk1, base);

	clk_register_clkdev(clk, "pll1_sysclk1", "dm644x-psc");
@@ -66,9 +67,9 @@ static const struct davinci_pll_clk_info dm644x_pll2_info = { 
SYSCLK(1, pll2_sysclk1, pll2_pllen, 4, 0);

SYSCLK(2, pll2_sysclk2, pll2_pllen, 4, 0);



int dm644x_pll2_init(struct device *dev, void __iomem *base)

int dm644x_pll2_init(struct device *dev, void __iomem *base, struct regmap *cfgchip)

{

	davinci_pll_clk_register(dev, &dm644x_pll2_info, "oscin", base);

	davinci_pll_clk_register(dev, &dm644x_pll2_info, "oscin", base, cfgchip);



	davinci_pll_sysclk_register(dev, &pll2_sysclk1, base);