Loading qcom/kona.dtsi +23 −0 Original line number Diff line number Diff line Loading @@ -3013,6 +3013,29 @@ }; }; ufs_ice: ufsice@1d90000 { compatible = "qcom,ice"; reg = <0x1d90000 0x8000>; qcom,enable-ice-clk; clock-names = "ufs_core_clk", "bus_clk", "iface_clk", "ice_core_clk"; clocks = <&clock_gcc GCC_UFS_PHY_AXI_CLK>, <&clock_gcc GCC_UFS_1X_CLKREF_EN>, <&clock_gcc GCC_UFS_PHY_AHB_CLK>, <&clock_gcc GCC_UFS_PHY_ICE_CORE_CLK>; qcom,op-freq-hz = <0>, <0>, <0>, <300000000>; vdd-hba-supply = <&ufs_phy_gdsc>; qcom,msm-bus,name = "ufs_ice_noc"; qcom,msm-bus,num-cases = <2>; qcom,msm-bus,num-paths = <1>; qcom,msm-bus,vectors-KBps = <1 650 0 0>, /* No vote */ <1 650 1000 0>; /* Max. bandwidth */ qcom,bus-vector-names = "MIN", "MAX"; qcom,instance-type = "ufs"; }; ufsphy_mem: ufsphy_mem@1d87000 { reg = <0x1d87000 0xe00>, <0x1d90000 0x8000>; /* PHY regs */ reg-names = "phy_mem", "ufs_ice"; Loading Loading
qcom/kona.dtsi +23 −0 Original line number Diff line number Diff line Loading @@ -3013,6 +3013,29 @@ }; }; ufs_ice: ufsice@1d90000 { compatible = "qcom,ice"; reg = <0x1d90000 0x8000>; qcom,enable-ice-clk; clock-names = "ufs_core_clk", "bus_clk", "iface_clk", "ice_core_clk"; clocks = <&clock_gcc GCC_UFS_PHY_AXI_CLK>, <&clock_gcc GCC_UFS_1X_CLKREF_EN>, <&clock_gcc GCC_UFS_PHY_AHB_CLK>, <&clock_gcc GCC_UFS_PHY_ICE_CORE_CLK>; qcom,op-freq-hz = <0>, <0>, <0>, <300000000>; vdd-hba-supply = <&ufs_phy_gdsc>; qcom,msm-bus,name = "ufs_ice_noc"; qcom,msm-bus,num-cases = <2>; qcom,msm-bus,num-paths = <1>; qcom,msm-bus,vectors-KBps = <1 650 0 0>, /* No vote */ <1 650 1000 0>; /* Max. bandwidth */ qcom,bus-vector-names = "MIN", "MAX"; qcom,instance-type = "ufs"; }; ufsphy_mem: ufsphy_mem@1d87000 { reg = <0x1d87000 0xe00>, <0x1d90000 0x8000>; /* PHY regs */ reg-names = "phy_mem", "ufs_ice"; Loading