Merge "mmc: sdhci-msm: Use correct register for toggling FIFO write clk" (75829fdf) · Commits · e / devices / android_kernel_oneplus_sm7250

drivers/mmc/host/sdhci-msm.c

+29 −0

Original line number	Diff line number	Diff line
		@@ -167,6 +167,8 @@
		#define MAX_DRV_TYPES_SUPPORTED_HS200 4
		#define MSM_AUTOSUSPEND_DELAY_MS 100

		#define RCLK_TOGGLE 0x2

		struct sdhci_msm_offset {
		u32 CORE_MCI_DATA_CNT;
		u32 CORE_MCI_STATUS;
		@@ -3723,6 +3725,33 @@ static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
		\| CORE_HC_SELECT_IN_EN), host->ioaddr +
		msm_host_offset->CORE_VENDOR_SPEC);
		}
		/*
		* After MCLK ugating, toggle the FIFO write clock to get
		* the FIFO pointers and flags to valid state.
		*/
		if (msm_host->tuning_done \|\|
		(card && mmc_card_strobe(card) &&
		msm_host->enhanced_strobe)) {
		/*
		* set HC_REG_DLL_CONFIG_3[1] to select MCLK as
		* DLL input clock
		*/
		writel_relaxed(((readl_relaxed(host->ioaddr +
		msm_host_offset->CORE_DLL_CONFIG_3))
		\| RCLK_TOGGLE), host->ioaddr +
		msm_host_offset->CORE_DLL_CONFIG_3);
		/* ensure above write as toggling same bit quickly */
		wmb();
		udelay(2);
		/*
		* clear HC_REG_DLL_CONFIG_3[1] to select RCLK as
		* DLL input clock
		*/
		writel_relaxed(((readl_relaxed(host->ioaddr +
		msm_host_offset->CORE_DLL_CONFIG_3))
		& ~RCLK_TOGGLE), host->ioaddr +
		msm_host_offset->CORE_DLL_CONFIG_3);
		}
		if (!host->mmc->ios.old_rate && !msm_host->use_cdclp533) {
		/*
		* Poll on DLL_LOCK and DDR_DLL_LOCK bits in