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Commit 750dcdff authored by Yujun Zhang's avatar Yujun Zhang Committed by Gerrit - the friendly Code Review server
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dt-bindings: clock: add support for 10nm DSI PLL shadow clock 



Add clock id for 10nm DSI PLL shadow clocks, which will be
used during dynamic dsi clock switch.

CRs-Fixed: 2314658
Change-Id: Ifcbeeab2f85f36cb0e872bf1a9ffcdeb479fb9fa
Signed-off-by: default avatarSandeep Panda <spanda@codeaurora.org>
Signed-off-by: default avatarYujun Zhang <yujunzhang@codeaurora.org>
parent b53cdddc

include/dt-bindings/clock/mdss-10nm-pll-clk.h

+26 −10
Original line number Original line Diff line number Diff line
@@ -17,16 +17,32 @@ 
#define PCLK_SRC_MUX_0_CLK	7

#define PCLK_SRC_MUX_0_CLK	7

#define PCLK_SRC_0_CLK		8

#define PCLK_SRC_0_CLK		8

#define PCLK_MUX_0_CLK		9

#define PCLK_MUX_0_CLK		9

#define VCO_CLK_1		10

#define SHADOW_VCO_CLK_0		10

#define PLL_OUT_DIV_1_CLK	11

#define SHADOW_PLL_OUT_DIV_0_CLK	11

#define BITCLK_SRC_1_CLK	12

#define SHADOW_BITCLK_SRC_0_CLK		12

#define BYTECLK_SRC_1_CLK	13

#define SHADOW_BYTECLK_SRC_0_CLK	13

#define POST_BIT_DIV_1_CLK	14

#define SHADOW_POST_BIT_DIV_0_CLK	14

#define POST_VCO_DIV_1_CLK	15

#define SHADOW_POST_VCO_DIV_0_CLK	15

#define BYTECLK_MUX_1_CLK	16

#define SHADOW_PCLK_SRC_MUX_0_CLK	16

#define PCLK_SRC_MUX_1_CLK	17

#define SHADOW_PCLK_SRC_0_CLK		17

#define PCLK_SRC_1_CLK		18

#define VCO_CLK_1		18

#define PCLK_MUX_1_CLK		19

#define PLL_OUT_DIV_1_CLK	19

#define BITCLK_SRC_1_CLK	20

#define BYTECLK_SRC_1_CLK	21

#define POST_BIT_DIV_1_CLK	22

#define POST_VCO_DIV_1_CLK	23

#define BYTECLK_MUX_1_CLK	24

#define PCLK_SRC_MUX_1_CLK	25

#define PCLK_SRC_1_CLK		26

#define PCLK_MUX_1_CLK		27

#define SHADOW_VCO_CLK_1		28

#define SHADOW_PLL_OUT_DIV_1_CLK	29

#define SHADOW_BITCLK_SRC_1_CLK		30

#define SHADOW_BYTECLK_SRC_1_CLK	31

#define SHADOW_POST_BIT_DIV_1_CLK	32

#define SHADOW_POST_VCO_DIV_1_CLK	33

#define SHADOW_PCLK_SRC_MUX_1_CLK	34

#define SHADOW_PCLK_SRC_1_CLK		35





/* DP PLL clocks */

/* DP PLL clocks */

#define	DP_VCO_CLK	0

#define	DP_VCO_CLK	0