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Commit 74bd8004 authored by Mahesh Kumar's avatar Mahesh Kumar Committed by Rodrigo Vivi
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drm/i915/icl: track dbuf slice-2 status 



This patch adds support to start tracking status of DBUF slices.
This is foundation to introduce support for enabling/disabling second
DBUF slice dynamically for ICL.

Changes Since V1:
 - use kernel type u8 over uint8_t

Signed-off-by: default avatarMahesh Kumar <mahesh1.kumar@intel.com>
Reviewed-by: default avatarJames Ausmus <james.ausmus@intel.com>
Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180426142517.16643-2-mahesh1.kumar@intel.com
parent 077ef1f0

drivers/gpu/drm/i915/i915_drv.h

+1 −0
Original line number Diff line number Diff line
@@ -1189,6 +1189,7 @@ struct skl_ddb_allocation { 
	/* packed/y */

	struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES];

	struct skl_ddb_entry uv_plane[I915_MAX_PIPES][I915_MAX_PLANES];

	u8 enabled_slices; /* GEN11 has configurable 2 slices */

};



struct skl_ddb_values {

drivers/gpu/drm/i915/intel_display.c

+5 −0
Original line number Diff line number Diff line
@@ -11447,6 +11447,11 @@ static void verify_wm_state(struct drm_crtc *crtc, 
	skl_ddb_get_hw_state(dev_priv, &hw_ddb);

	sw_ddb = &dev_priv->wm.skl_hw.ddb;



	if (INTEL_GEN(dev_priv) >= 11)

		if (hw_ddb.enabled_slices != sw_ddb->enabled_slices)

			DRM_ERROR("mismatch in DBUF Slices (expected %u, got %u)\n",

				  sw_ddb->enabled_slices,

				  hw_ddb.enabled_slices);

	/* planes */

	for_each_universal_plane(dev_priv, pipe, plane) {

		hw_plane_wm = &hw_wm.planes[plane];

drivers/gpu/drm/i915/intel_pm.c

+20 −0
Original line number Diff line number Diff line
@@ -3567,6 +3567,23 @@ bool ilk_disable_lp_wm(struct drm_device *dev) 
	return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);

}



static u8 intel_enabled_dbuf_slices_num(struct drm_i915_private *dev_priv)

{

	u8 enabled_slices;



	/* Slice 1 will always be enabled */

	enabled_slices = 1;



	/* Gen prior to GEN11 have only one DBuf slice */

	if (INTEL_GEN(dev_priv) < 11)

		return enabled_slices;



	if (I915_READ(DBUF_CTL_S2) & DBUF_POWER_STATE)

		enabled_slices++;



	return enabled_slices;

}



/*

 * FIXME: We still don't have the proper code detect if we need to apply the WA,

 * so assume we'll always need it in order to avoid underruns.
@@ -3870,6 +3887,8 @@ void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv, 


	memset(ddb, 0, sizeof(*ddb));



	ddb->enabled_slices = intel_enabled_dbuf_slices_num(dev_priv);



	for_each_intel_crtc(&dev_priv->drm, crtc) {

		enum intel_display_power_domain power_domain;

		enum plane_id plane_id;
@@ -5088,6 +5107,7 @@ skl_copy_ddb_for_pipe(struct skl_ddb_values *dst, 
	       sizeof(dst->ddb.uv_plane[pipe]));

	memcpy(dst->ddb.plane[pipe], src->ddb.plane[pipe],

	       sizeof(dst->ddb.plane[pipe]));

	dst->ddb.enabled_slices = src->ddb.enabled_slices;

}



static void

drivers/gpu/drm/i915/intel_runtime_pm.c

+4 −0
Original line number Diff line number Diff line
@@ -2656,6 +2656,8 @@ static void icl_dbuf_enable(struct drm_i915_private *dev_priv) 
	if (!(I915_READ(DBUF_CTL_S1) & DBUF_POWER_STATE) ||

	    !(I915_READ(DBUF_CTL_S2) & DBUF_POWER_STATE))

		DRM_ERROR("DBuf power enable timeout\n");

	else

		dev_priv->wm.skl_hw.ddb.enabled_slices = 2;

}



static void icl_dbuf_disable(struct drm_i915_private *dev_priv)
@@ -2669,6 +2671,8 @@ static void icl_dbuf_disable(struct drm_i915_private *dev_priv) 
	if ((I915_READ(DBUF_CTL_S1) & DBUF_POWER_STATE) ||

	    (I915_READ(DBUF_CTL_S2) & DBUF_POWER_STATE))

		DRM_ERROR("DBuf power disable timeout!\n");

	else

		dev_priv->wm.skl_hw.ddb.enabled_slices = 0;

}



static void icl_mbus_init(struct drm_i915_private *dev_priv)