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Commit 74894363 authored by Atsushi Nemoto's avatar Atsushi Nemoto Committed by Ralf Baechle
Browse files

MIPS: TXx9: Raise priority of interrupts for errors, timers, SIO 



Signed-off-by: default avatarAtsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 51f607c7

arch/mips/txx9/generic/irq_tx4927.c

+11 −0
Original line number Diff line number Diff line
@@ -30,8 +30,19 @@ 


void __init tx4927_irq_init(void)

{

	int i;



	mips_cpu_irq_init();

	txx9_irq_init(TX4927_IRC_REG & 0xfffffffffULL);

	set_irq_chained_handler(MIPS_CPU_IRQ_BASE + TX4927_IRC_INT,

				handle_simple_irq);

	/* raise priority for errors, timers, SIO */

	txx9_irq_set_pri(TX4927_IR_ECCERR, 7);

	txx9_irq_set_pri(TX4927_IR_WTOERR, 7);

	txx9_irq_set_pri(TX4927_IR_PCIERR, 7);

	txx9_irq_set_pri(TX4927_IR_PCIPME, 7);

	for (i = 0; i < TX4927_NUM_IR_TMR; i++)

		txx9_irq_set_pri(TX4927_IR_TMR(i), 6);

	for (i = 0; i < TX4927_NUM_IR_SIO; i++)

		txx9_irq_set_pri(TX4927_IR_SIO(i), 5);

}

arch/mips/txx9/generic/irq_tx4938.c

+11 −0
Original line number Diff line number Diff line
@@ -18,8 +18,19 @@ 


void __init tx4938_irq_init(void)

{

	int i;



	mips_cpu_irq_init();

	txx9_irq_init(TX4938_IRC_REG & 0xfffffffffULL);

	set_irq_chained_handler(MIPS_CPU_IRQ_BASE + TX4938_IRC_INT,

				handle_simple_irq);

	/* raise priority for errors, timers, SIO */

	txx9_irq_set_pri(TX4938_IR_ECCERR, 7);

	txx9_irq_set_pri(TX4938_IR_WTOERR, 7);

	txx9_irq_set_pri(TX4938_IR_PCIERR, 7);

	txx9_irq_set_pri(TX4938_IR_PCIPME, 7);

	for (i = 0; i < TX4938_NUM_IR_TMR; i++)

		txx9_irq_set_pri(TX4938_IR_TMR(i), 6);

	for (i = 0; i < TX4938_NUM_IR_SIO; i++)

		txx9_irq_set_pri(TX4938_IR_SIO(i), 5);

}

include/asm-mips/txx9/tx4927.h

+11 −0
Original line number Diff line number Diff line
@@ -50,12 +50,23 @@ 
#define TX4927_SIO_REG(ch)	(TX4927_REG_BASE + 0xf300 + (ch) * 0x100)

#define TX4927_PIO_REG		(TX4927_REG_BASE + 0xf500)



#define TX4927_IR_ECCERR	0

#define TX4927_IR_WTOERR	1

#define TX4927_NUM_IR_INT	6

#define TX4927_IR_INT(n)	(2 + (n))

#define TX4927_NUM_IR_SIO	2

#define TX4927_IR_SIO(n)	(8 + (n))

#define TX4927_NUM_IR_DMA	4

#define TX4927_IR_DMA(n)	(10 + (n))

#define TX4927_IR_PIO		14

#define TX4927_IR_PDMAC		15

#define TX4927_IR_PCIC		16

#define TX4927_NUM_IR_TMR	3

#define TX4927_IR_TMR(n)	(17 + (n))

#define TX4927_IR_PCIERR	22

#define TX4927_IR_PCIPME	23

#define TX4927_IR_ACLC		24

#define TX4927_IR_ACLCPME	25

#define TX4927_NUM_IR	32



#define TX4927_IRC_INT	2	/* IP[2] in Status register */