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Commit 74419daa authored by Daniele Ceraolo Spurio's avatar Daniele Ceraolo Spurio Committed by Chris Wilson
Browse files

drm/i915: add a selftest for the mmio_bases table 



Check that the entries are in reverse gen order and that all entries
with gen > 0 have an mmio base set.

v2: loop forward, simplify logic, use i915_subtests (Chris)

Suggested-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: default avatarDaniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20180314182653.26981-2-daniele.ceraolospurio@intel.com
parent 80b216b9

drivers/gpu/drm/i915/intel_engine_cs.c

+10 −6
Original line number Diff line number Diff line
@@ -263,16 +263,21 @@ static u32 __engine_mmio_base(struct drm_i915_private *i915, 
	return bases[i].base;

}



static void __sprint_engine_name(char *name, const struct engine_info *info)

{

	WARN_ON(snprintf(name, INTEL_ENGINE_CS_MAX_NAME, "%s%u",

			 intel_engine_classes[info->class].name,

			 info->instance) >= INTEL_ENGINE_CS_MAX_NAME);

}



static int

intel_engine_setup(struct drm_i915_private *dev_priv,

		   enum intel_engine_id id)

{

	const struct engine_info *info = &intel_engines[id];

	const struct engine_class_info *class_info;

	struct intel_engine_cs *engine;



	GEM_BUG_ON(info->class >= ARRAY_SIZE(intel_engine_classes));

	class_info = &intel_engine_classes[info->class];



	BUILD_BUG_ON(MAX_ENGINE_CLASS >= BIT(GEN11_ENGINE_CLASS_WIDTH));

	BUILD_BUG_ON(MAX_ENGINE_INSTANCE >= BIT(GEN11_ENGINE_INSTANCE_WIDTH));
@@ -293,9 +298,7 @@ intel_engine_setup(struct drm_i915_private *dev_priv, 


	engine->id = id;

	engine->i915 = dev_priv;

	WARN_ON(snprintf(engine->name, sizeof(engine->name), "%s%u",

			 class_info->name, info->instance) >=

		sizeof(engine->name));

	__sprint_engine_name(engine->name, info);

	engine->hw_id = engine->guc_id = info->hw_id;

	engine->mmio_base = __engine_mmio_base(dev_priv, info->mmio_bases);

	engine->irq_shift = info->irq_shift;
@@ -303,7 +306,7 @@ intel_engine_setup(struct drm_i915_private *dev_priv, 
	engine->instance = info->instance;



	engine->uabi_id = info->uabi_id;

	engine->uabi_class = class_info->uabi_class;

	engine->uabi_class = intel_engine_classes[info->class].uabi_class;



	engine->context_size = __intel_engine_context_size(dev_priv,

							   engine->class);
@@ -2140,4 +2143,5 @@ void intel_disable_engine_stats(struct intel_engine_cs *engine) 


#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)

#include "selftests/mock_engine.c"

#include "selftests/intel_engine_cs.c"

#endif

drivers/gpu/drm/i915/selftests/i915_mock_selftests.h

+1 −0
Original line number Diff line number Diff line
@@ -14,6 +14,7 @@ selftest(fence, i915_sw_fence_mock_selftests) 
selftest(scatterlist, scatterlist_mock_selftests)

selftest(syncmap, i915_syncmap_mock_selftests)

selftest(uncore, intel_uncore_mock_selftests)

selftest(engine, intel_engine_cs_mock_selftests)

selftest(breadcrumbs, intel_breadcrumbs_mock_selftests)

selftest(timelines, i915_gem_timeline_mock_selftests)

selftest(requests, i915_request_mock_selftests)

drivers/gpu/drm/i915/selftests/intel_engine_cs.c

0 → 100644
+58 −0
Original line number Diff line number Diff line 
/*

 * SPDX-License-Identifier: GPL-2.0

 *

 * Copyright © 2018 Intel Corporation

 */



#include "../i915_selftest.h"



static int intel_mmio_bases_check(void *arg)

{

	int i, j;



	for (i = 0; i < ARRAY_SIZE(intel_engines); i++) {

		const struct engine_info *info = &intel_engines[i];

		char name[INTEL_ENGINE_CS_MAX_NAME];

		u8 prev = U8_MAX;



		__sprint_engine_name(name, info);



		for (j = 0; j < MAX_MMIO_BASES; j++) {

			u8 gen = info->mmio_bases[j].gen;

			u32 base = info->mmio_bases[j].base;



			if (gen >= prev) {

				pr_err("%s: %s: mmio base for gen %x "

					"is before the one for gen %x\n",

				       __func__, name, prev, gen);

				return -EINVAL;

			}



			if (gen == 0)

				break;



			if (!base) {

				pr_err("%s: %s: invalid mmio base (%x) "

					"for gen %x at entry %u\n",

				       __func__, name, base, gen, j);

				return -EINVAL;

			}



			prev = gen;

		}



		pr_info("%s: min gen supported for %s = %d\n",

			__func__, name, prev);

	}



	return 0;

}



int intel_engine_cs_mock_selftests(void)

{

	static const struct i915_subtest tests[] = {

		SUBTEST(intel_mmio_bases_check),

	};



	return i915_subtests(tests, NULL);

}