Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 741972d8 authored by Andre Przywara's avatar Andre Przywara Committed by Christoffer Dall
Browse files

KVM: arm/arm64: vgic-new: Add GICv3 redistributor IIDR and TYPER handler 



The redistributor TYPER tells the OS about the associated MPIDR,
also the LAST bit is crucial to determine the number of redistributors.

Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
Reviewed-by: default avatarChristoffer Dall <christoffer.dall@linaro.org>
parent fd59ed3b

virt/kvm/arm/vgic/vgic-mmio-v3.c

+30 −2
Original line number Original line Diff line number Diff line
@@ -22,6 +22,13 @@ 
#include "vgic.h"

#include "vgic.h"

#include "vgic-mmio.h"

#include "vgic-mmio.h"





/* extract @num bytes at @offset bytes offset in data */

static unsigned long extract_bytes(unsigned long data, unsigned int offset,

				   unsigned int num)

{

	return (data >> (offset * 8)) & GENMASK_ULL(num * 8 - 1, 0);

}



static unsigned long vgic_mmio_read_v3_misc(struct kvm_vcpu *vcpu,

static unsigned long vgic_mmio_read_v3_misc(struct kvm_vcpu *vcpu,

					    gpa_t addr, unsigned int len)

					    gpa_t addr, unsigned int len)

{

{
@@ -68,6 +75,27 @@ static void vgic_mmio_write_v3_misc(struct kvm_vcpu *vcpu, 
	}

	}

}

}





static unsigned long vgic_mmio_read_v3r_typer(struct kvm_vcpu *vcpu,

					      gpa_t addr, unsigned int len)

{

	unsigned long mpidr = kvm_vcpu_get_mpidr_aff(vcpu);

	int target_vcpu_id = vcpu->vcpu_id;

	u64 value;



	value = (mpidr & GENMASK(23, 0)) << 32;

	value |= ((target_vcpu_id & 0xffff) << 8);

	if (target_vcpu_id == atomic_read(&vcpu->kvm->online_vcpus) - 1)

		value |= GICR_TYPER_LAST;



	return extract_bytes(value, addr & 7, len);

}



static unsigned long vgic_mmio_read_v3r_iidr(struct kvm_vcpu *vcpu,

					     gpa_t addr, unsigned int len)

{

	return (PRODUCT_ID_KVM << 24) | (IMPLEMENTER_ARM << 0);

}



/*

/*

 * The GICv3 per-IRQ registers are split to control PPIs and SGIs in the

 * The GICv3 per-IRQ registers are split to control PPIs and SGIs in the

 * redistributors, while SPIs are covered by registers in the distributor

 * redistributors, while SPIs are covered by registers in the distributor
@@ -142,10 +170,10 @@ static const struct vgic_register_region vgic_v3_rdbase_registers[] = { 
		vgic_mmio_read_raz, vgic_mmio_write_wi, 4,

		vgic_mmio_read_raz, vgic_mmio_write_wi, 4,

		VGIC_ACCESS_32bit),

		VGIC_ACCESS_32bit),

	REGISTER_DESC_WITH_LENGTH(GICR_IIDR,

	REGISTER_DESC_WITH_LENGTH(GICR_IIDR,

		vgic_mmio_read_raz, vgic_mmio_write_wi, 4,

		vgic_mmio_read_v3r_iidr, vgic_mmio_write_wi, 4,

		VGIC_ACCESS_32bit),

		VGIC_ACCESS_32bit),

	REGISTER_DESC_WITH_LENGTH(GICR_TYPER,

	REGISTER_DESC_WITH_LENGTH(GICR_TYPER,

		vgic_mmio_read_raz, vgic_mmio_write_wi, 8,

		vgic_mmio_read_v3r_typer, vgic_mmio_write_wi, 8,

		VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),

		VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),

	REGISTER_DESC_WITH_LENGTH(GICR_PROPBASER,

	REGISTER_DESC_WITH_LENGTH(GICR_PROPBASER,

		vgic_mmio_read_raz, vgic_mmio_write_wi, 8,

		vgic_mmio_read_raz, vgic_mmio_write_wi, 8,