Commit 74124439 authored Jan 21, 2016 by Chen-Yu Tsai Committed by Maxime Ripard Jan 25, 2016

ARM: dts: sun8i: sina33: Enable hardware reset and HS-DDR for eMMC



mmc2 has a special pin for eMMC hardware reset, which is controllable
from the controller. Add the "mmc-cap-hw-reset" property to denote that
this controller supports this function, and the pins are actually used.

Also increase the signal drive strength for mmc2 pins, for HS-DDR mode
support.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

parent db30fce1

arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts

+3 −0

Original line number	Diff line number	Diff line
		@@ -109,10 +109,13 @@
		vmmc-supply = <&reg_vcc3v0>;
		bus-width = <8>;
		non-removable;
		cap-mmc-hw-reset;
		status = "okay";
		};

		&mmc2_8bit_pins {
		/* Increase drive strength for DDR modes */
		allwinner,drive = <SUN4I_PINCTRL_40_MA>;
		/* eMMC is missing pull-ups */
		allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
		};