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Commit 736add24 authored by Marcin Nowakowski's avatar Marcin Nowakowski Committed by Ralf Baechle
Browse files

MIPS: perf: add I6500 handling 



Add a definition of the perf registers for the new I6500 core.

Since I6500 has the same event definitions as I6400, re-use the existing
i6400 map structures by renaming them to a slightly more generic
'i6x00_***_map'.

Signed-off-by: default avatarMarcin Nowakowski <marcin.nowakowski@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/16362/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 859aeb1b

arch/mips/kernel/perf_event_mipsxx.c

+10 −4
Original line number Diff line number Diff line
@@ -814,7 +814,7 @@ static const struct mips_perf_event mipsxxcore_event_map2 
	[PERF_COUNT_HW_BRANCH_MISSES] = { 0x27, CNTR_ODD, T },

};



static const struct mips_perf_event i6400_event_map[PERF_COUNT_HW_MAX] = {

static const struct mips_perf_event i6x00_event_map[PERF_COUNT_HW_MAX] = {

	[PERF_COUNT_HW_CPU_CYCLES]          = { 0x00, CNTR_EVEN | CNTR_ODD },

	[PERF_COUNT_HW_INSTRUCTIONS]        = { 0x01, CNTR_EVEN | CNTR_ODD },

	/* These only count dcache, not icache */
@@ -1014,7 +1014,7 @@ static const struct mips_perf_event mipsxxcore_cache_map2 
},

};



static const struct mips_perf_event i6400_cache_map

static const struct mips_perf_event i6x00_cache_map

				[PERF_COUNT_HW_CACHE_MAX]

				[PERF_COUNT_HW_CACHE_OP_MAX]

				[PERF_COUNT_HW_CACHE_RESULT_MAX] = {
@@ -1610,6 +1610,7 @@ static const struct mips_perf_event *mipsxx_pmu_map_raw_event(u64 config) 
#endif

		break;

	case CPU_I6400:

	case CPU_I6500:

		/* 8-bit event numbers */

		base_id = config & 0xff;

		raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
@@ -1770,8 +1771,13 @@ init_hw_perf_events(void) 
		break;

	case CPU_I6400:

		mipspmu.name = "mips/I6400";

		mipspmu.general_event_map = &i6400_event_map;

		mipspmu.cache_event_map = &i6400_cache_map;

		mipspmu.general_event_map = &i6x00_event_map;

		mipspmu.cache_event_map = &i6x00_cache_map;

		break;

	case CPU_I6500:

		mipspmu.name = "mips/I6500";

		mipspmu.general_event_map = &i6x00_event_map;

		mipspmu.cache_event_map = &i6x00_cache_map;

		break;

	case CPU_1004K:

		mipspmu.name = "mips/1004K";