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Commit 72fc36b6 authored by Mario Smarduch's avatar Mario Smarduch Committed by Christoffer Dall
Browse files

KVM: arm: Add ARMv7 API to flush TLBs 



This patch adds ARMv7 architecture TLB Flush function.

Acked-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
Acked-by: default avatarChristoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: default avatarMario Smarduch <m.smarduch@samsung.com>
parent e108ff2f

arch/arm/include/asm/kvm_asm.h

+1 −0
Original line number Diff line number Diff line
@@ -96,6 +96,7 @@ extern char __kvm_hyp_code_end[]; 


extern void __kvm_flush_vm_context(void);

extern void __kvm_tlb_flush_vmid_ipa(struct kvm *kvm, phys_addr_t ipa);

extern void __kvm_tlb_flush_vmid(struct kvm *kvm);



extern int __kvm_vcpu_run(struct kvm_vcpu *vcpu);

#endif

arch/arm/include/asm/kvm_host.h

+12 −0
Original line number Diff line number Diff line
@@ -221,6 +221,18 @@ static inline void __cpu_init_hyp_mode(phys_addr_t boot_pgd_ptr, 
	kvm_call_hyp((void*)hyp_stack_ptr, vector_ptr, pgd_ptr);

}



/**

 * kvm_flush_remote_tlbs() - flush all VM TLB entries

 * @kvm:	pointer to kvm structure.

 *

 * Interface to HYP function to flush all VM TLB entries without address

 * parameter.

 */

static inline void kvm_flush_remote_tlbs(struct kvm *kvm)

{

	kvm_call_hyp(__kvm_tlb_flush_vmid, kvm);

}



static inline int kvm_arch_dev_ioctl_check_extension(long ext)

{

	return 0;

arch/arm/kvm/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -21,6 +21,7 @@ config KVM 
	select PREEMPT_NOTIFIERS

	select ANON_INODES

	select HAVE_KVM_CPU_RELAX_INTERCEPT

	select HAVE_KVM_ARCH_TLB_FLUSH_ALL

	select KVM_MMIO

	select KVM_ARM_HOST

	depends on ARM_VIRT_EXT && ARM_LPAE

arch/arm/kvm/interrupts.S

+11 −0
Original line number Diff line number Diff line
@@ -66,6 +66,17 @@ ENTRY(__kvm_tlb_flush_vmid_ipa) 
	bx	lr

ENDPROC(__kvm_tlb_flush_vmid_ipa)



/**

 * void __kvm_tlb_flush_vmid(struct kvm *kvm) - Flush per-VMID TLBs

 *

 * Reuses __kvm_tlb_flush_vmid_ipa() for ARMv7, without passing address

 * parameter

 */



ENTRY(__kvm_tlb_flush_vmid)

	b	__kvm_tlb_flush_vmid_ipa

ENDPROC(__kvm_tlb_flush_vmid)



/********************************************************************

 * Flush TLBs and instruction caches of all CPUs inside the inner-shareable

 * domain, for all VMIDs