Merge "clk: qcom: gpucc: Update the post div ops for GPUCC PLL for KHAJE" (72d68d0d) · Commits · e / devices / android_kernel_oneplus_sm7250

drivers/clk/qcom/clk-alpha-pll.c

+37 −4

Original line number	Diff line number	Diff line
		@@ -510,6 +510,19 @@ alpha_pll_calc_rate(u64 prate, u32 l, u32 a, u32 alpha_width)
		return (prate * l) + ((prate * a) >> ALPHA_SHIFT(alpha_width));
		}

		static void zonda_pll_adjust_l_val(unsigned long rate, unsigned long prate,
		u32 *l)
		{
		u64 remainder, quotient;

		quotient = rate;
		remainder = do_div(quotient, prate);
		*l = quotient;

		if ((remainder * 2) / prate)
		l = l + 1;
		}

		static unsigned long
		alpha_pll_round_rate(unsigned long rate, unsigned long prate, u32 l, u64 a,
		u32 alpha_width)
		@@ -1311,6 +1324,7 @@ static int clk_zonda_pll_set_rate(struct clk_hw *hw, unsigned long rate,
		int ret;

		rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width);

		/*
		* Due to a limited number of bits for fractional rate programming, the
		* rounded up rate could be marginally higher than the requested rate.
		@@ -1321,6 +1335,9 @@ static int clk_zonda_pll_set_rate(struct clk_hw *hw, unsigned long rate,
		return -EINVAL;
		}

		if (a && (a & BIT(15)))
		zonda_pll_adjust_l_val(rate, prate, &l);

		regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
		regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);

		@@ -1348,6 +1365,19 @@ static int clk_zonda_pll_set_rate(struct clk_hw *hw, unsigned long rate,
		return 0;
		}

		static unsigned long alpha_pll_adjust_calc_rate(u64 prate, u32 l, u32 frac,
		u32 alpha_width)
		{
		uint64_t tmp;

		frac = 100 - DIV_ROUND_UP_ULL((frac * 100), BIT(alpha_width));

		tmp = frac * prate;
		do_div(tmp, 100);

		return (l * prate) - tmp;
		}

		static unsigned long
		clk_zonda_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
		{
		@@ -1357,6 +1387,10 @@ clk_zonda_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
		regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l);
		regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &frac);

		if (frac & BIT(15))
		return alpha_pll_adjust_calc_rate(parent_rate, l, frac,
		alpha_width);
		else
		return alpha_pll_calc_rate(parent_rate, l, frac, alpha_width);
		}

		@@ -2687,7 +2721,6 @@ static int clk_alpha_pll_calibrate(struct clk_hw *hw)
		freq_hz = alpha_pll_round_rate(clk_hw_get_rate(hw),
		clk_hw_get_rate(parent), &l, &a, alpha_width);


		pr_debug("pll %s: setting back to required rate %lu, freq_hz %ld\n",
		hw->init->name, clk_hw_get_rate(hw), freq_hz);

drivers/clk/qcom/gpucc-khaje.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -130,7 +130,7 @@ static struct clk_alpha_pll_postdiv gpu_cc_pll0_out_main = {
		.parent_names = (const char *[]){ "gpu_cc_pll0" },
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
		.ops = &clk_alpha_pll_postdiv_zonda_ops,
		.ops = &clk_alpha_pll_postdiv_ro_ops,
		},
		};