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Commit 72cde5a8 authored by Paul Mackerras's avatar Paul Mackerras
Browse files

KVM: PPC: Book3S HV: Save/restore host PMU registers that are new in POWER8 



Currently we save the host PMU configuration, counter values, etc.,
when entering a guest, and restore it on return from the guest.
(We have to do this because the guest has control of the PMU while
it is executing.)  However, we missed saving/restoring the SIAR and
SDAR registers, as well as the registers which are new on POWER8,
namely SIER and MMCR2.

This adds code to save the values of these registers when entering
the guest and restore them on exit.  This also works around the bug
in POWER8 where setting PMAE with a counter already negative doesn't
generate an interrupt.

Signed-off-by: default avatarPaul Mackerras <paulus@samba.org>
Acked-by: default avatarScott Wood <scottwood@freescale.com>
parent c5fb80d3

arch/powerpc/include/asm/kvm_book3s_asm.h

+1 −1
Original line number Diff line number Diff line
@@ -94,7 +94,7 @@ struct kvmppc_host_state { 
	unsigned long xics_phys;

	u32 saved_xirr;

	u64 dabr;

	u64 host_mmcr[3];

	u64 host_mmcr[7];	/* MMCR 0,1,A, SIAR, SDAR, MMCR2, SIER */

	u32 host_pmc[8];

	u64 host_purr;

	u64 host_spurr;

arch/powerpc/kvm/book3s_hv_interrupts.S

+22 −0
Original line number Diff line number Diff line
@@ -71,6 +71,14 @@ END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S) 
	mtmsrd  r10,1



	/* Save host PMU registers */

BEGIN_FTR_SECTION

	/* Work around P8 PMAE bug */

	li	r3, -1

	clrrdi	r3, r3, 10

	mfspr	r8, SPRN_MMCR2

	mtspr	SPRN_MMCR2, r3		/* freeze all counters using MMCR2 */

	isync

END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)

	li	r3, 1

	sldi	r3, r3, 31		/* MMCR0_FC (freeze counters) bit */

	mfspr	r7, SPRN_MMCR0		/* save MMCR0 */
@@ -87,9 +95,18 @@ END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206) 
	cmpwi	r5, 0

	beq	31f			/* skip if not */

	mfspr	r5, SPRN_MMCR1

	mfspr	r9, SPRN_SIAR

	mfspr	r10, SPRN_SDAR

	std	r7, HSTATE_MMCR(r13)

	std	r5, HSTATE_MMCR + 8(r13)

	std	r6, HSTATE_MMCR + 16(r13)

	std	r9, HSTATE_MMCR + 24(r13)

	std	r10, HSTATE_MMCR + 32(r13)

BEGIN_FTR_SECTION

	mfspr	r9, SPRN_SIER

	std	r8, HSTATE_MMCR + 40(r13)

	std	r9, HSTATE_MMCR + 48(r13)

END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)

	mfspr	r3, SPRN_PMC1

	mfspr	r5, SPRN_PMC2

	mfspr	r6, SPRN_PMC3
@@ -110,6 +127,11 @@ BEGIN_FTR_SECTION 
	stw	r10, HSTATE_PMC + 24(r13)

	stw	r11, HSTATE_PMC + 28(r13)

END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)

BEGIN_FTR_SECTION

	mfspr	r9, SPRN_SIER

	std	r8, HSTATE_MMCR + 40(r13)

	std	r9, HSTATE_MMCR + 48(r13)

END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)

31:



	/*

arch/powerpc/kvm/book3s_hv_rmhandlers.S

+10 −0
Original line number Diff line number Diff line
@@ -109,8 +109,18 @@ END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201) 
	ld	r3, HSTATE_MMCR(r13)

	ld	r4, HSTATE_MMCR + 8(r13)

	ld	r5, HSTATE_MMCR + 16(r13)

	ld	r6, HSTATE_MMCR + 24(r13)

	ld	r7, HSTATE_MMCR + 32(r13)

	mtspr	SPRN_MMCR1, r4

	mtspr	SPRN_MMCRA, r5

	mtspr	SPRN_SIAR, r6

	mtspr	SPRN_SDAR, r7

BEGIN_FTR_SECTION

	ld	r8, HSTATE_MMCR + 40(r13)

	ld	r9, HSTATE_MMCR + 48(r13)

	mtspr	SPRN_MMCR2, r8

	mtspr	SPRN_SIER, r9

END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)

	mtspr	SPRN_MMCR0, r3

	isync

23: