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Commit 72a69861 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: Add CTI config for ETB and ETR for lito"

parents c9a0ebcf 9bfe9f08

qcom/lito-coresight.dtsi

+2 −1
Original line number Diff line number Diff line
@@ -104,6 +104,7 @@ 
		reg-names = "tmc-base";



		coresight-name = "coresight-tmc-etf";

		coresight-ctis = <&cti0_swao &cti3_swao>;

		coresight-csr = <&swao_csr>;

		clocks = <&aopcc QDSS_CLK>;

		clock-names = "apb_pclk";
@@ -300,7 +301,7 @@ 


		qcom,sw-usb;

		coresight-name = "coresight-tmc-etr";

		coresight-ctis = <&cti0 &cti0>;

		coresight-ctis = <&cti0 &cti3_swao>;

		coresight-csr = <&csr>;



		clocks = <&aopcc QDSS_CLK>;