Merge tag 'irqchip-4.17' of...

			of a GICv2 controller even if the memory range

			exposed by the device tree is too small.

	irqchip.gicv3_nolpi=

			[ARM, ARM64]

			Force the kernel to ignore the availability of

			LPIs (and by consequence ITSs). Intended for system

			that use the kernel as a bootloader, and thus want

			to let secondary kernels in charge of setting up

			LPIs.

	irqfixup	[HW]

			When an interrupt is not handled search all handlers

			for it. Intended to get systems with badly broken

Microsemi Ocelot SoC ICPU Interrupt Controller

Required properties:

- compatible : should be "mscc,ocelot-icpu-intr"

- reg : Specifies base physical address and size of the registers.

- interrupt-controller : Identifies the node as an interrupt controller

- #interrupt-cells : Specifies the number of cells needed to encode an

  interrupt source. The value shall be 1.

- interrupt-parent : phandle of the CPU interrupt controller.

- interrupts : Specifies the CPU interrupt the controller is connected to.

Example:

		intc: interrupt-controller@70000070 {

			compatible = "mscc,ocelot-icpu-intr";

			reg = <0x70000070 0x70>;

			#interrupt-cells = <1>;

			interrupt-controller;

			interrupt-parent = <&cpuintc>;

			interrupts = <2>;

		};

PDC interrupt controller

Qualcomm Technologies Inc. SoCs based on the RPM Hardened architecture have a

Power Domain Controller (PDC) that is on always-on domain. In addition to

providing power control for the power domains, the hardware also has an

interrupt controller that can be used to help detect edge low interrupts as

well detect interrupts when the GIC is non-operational.

GIC is parent interrupt controller at the highest level. Platform interrupt

controller PDC is next in hierarchy, followed by others. Drivers requiring

wakeup capabilities of their device interrupts routed through the PDC, must

specify PDC as their interrupt controller and request the PDC port associated

with the GIC interrupt. See example below.

Properties:

- compatible:

	Usage: required

	Value type: <string>

	Definition: Should contain "qcom,<soc>-pdc"

		    - "qcom,sdm845-pdc": For SDM845

- reg:

	Usage: required

	Value type: <prop-encoded-array>

	Definition: Specifies the base physical address for PDC hardware.

- interrupt-cells:

	Usage: required

	Value type: <u32>

	Definition: Specifies the number of cells needed to encode an interrupt

		    source.

		    Must be 2.

		    The first element of the tuple is the PDC pin for the

		    interrupt.

		    The second element is the trigger type.

- interrupt-parent:

	Usage: required

	Value type: <phandle>

	Definition: Specifies the interrupt parent necessary for hierarchical

		    domain to operate.

- interrupt-controller:

	Usage: required

	Value type: <bool>

	Definition: Identifies the node as an interrupt controller.

- qcom,pdc-ranges:

	Usage: required

	Value type: <u32 array>

	Definition: Specifies the PDC pin offset and the number of PDC ports.

		    The tuples indicates the valid mapping of valid PDC ports

		    and their hwirq mapping.

		    The first element of the tuple is the starting PDC port.

		    The second element is the GIC hwirq number for the PDC port.

		    The third element is the number of interrupts in sequence.

Example:

	pdc: interrupt-controller@b220000 {

		compatible = "qcom,sdm845-pdc";

		reg = <0xb220000 0x30000>;

		qcom,pdc-ranges = <0 512 94>, <94 641 15>, <115 662 7>;

		#interrupt-cells = <2>;

		interrupt-parent = <&intc>;

		interrupt-controller;

	};

DT binding of a device that wants to use the GIC SPI 514 as a wakeup

interrupt, must do -

	wake-device {

		interrupts-extended = <&pdc 2 IRQ_TYPE_LEVEL_HIGH>;

	};

In this case interrupt 514 would be mapped to port 2 on the PDC as defined by

the qcom,pdc-ranges property.

#define ICC_IGRPEN1			__ACCESS_CP15(c12, 0, c12, 7)

#define ICC_BPR1			__ACCESS_CP15(c12, 0, c12, 3)

#define __ICC_AP0Rx(x)			__ACCESS_CP15(c12, 0, c8, 4 | x)

#define ICC_AP0R0			__ICC_AP0Rx(0)

#define ICC_AP0R1			__ICC_AP0Rx(1)

#define ICC_AP0R2			__ICC_AP0Rx(2)

#define ICC_AP0R3			__ICC_AP0Rx(3)

#define __ICC_AP1Rx(x)			__ACCESS_CP15(c12, 0, c9, x)

#define ICC_AP1R0			__ICC_AP1Rx(0)

#define ICC_AP1R1			__ICC_AP1Rx(1)

#define ICC_AP1R2			__ICC_AP1Rx(2)

#define ICC_AP1R3			__ICC_AP1Rx(3)

#define ICC_HSRE			__ACCESS_CP15(c12, 4, c9, 5)

#define ICH_VSEIR			__ACCESS_CP15(c12, 4, c9, 4)

#define ICH_LRC14			__LRC8(6)

#define ICH_LRC15			__LRC8(7)

#define __AP0Rx(x)			__ACCESS_CP15(c12, 4, c8, x)

#define ICH_AP0R0			__AP0Rx(0)

#define ICH_AP0R1			__AP0Rx(1)

#define ICH_AP0R2			__AP0Rx(2)

#define ICH_AP0R3			__AP0Rx(3)

#define __ICH_AP0Rx(x)			__ACCESS_CP15(c12, 4, c8, x)

#define ICH_AP0R0			__ICH_AP0Rx(0)

#define ICH_AP0R1			__ICH_AP0Rx(1)

#define ICH_AP0R2			__ICH_AP0Rx(2)

#define ICH_AP0R3			__ICH_AP0Rx(3)

#define __AP1Rx(x)			__ACCESS_CP15(c12, 4, c9, x)

#define ICH_AP1R0			__AP1Rx(0)

#define ICH_AP1R1			__AP1Rx(1)

#define ICH_AP1R2			__AP1Rx(2)

#define ICH_AP1R3			__AP1Rx(3)

#define __ICH_AP1Rx(x)			__ACCESS_CP15(c12, 4, c9, x)

#define ICH_AP1R0			__ICH_AP1Rx(0)

#define ICH_AP1R1			__ICH_AP1Rx(1)

#define ICH_AP1R2			__ICH_AP1Rx(2)

#define ICH_AP1R3			__ICH_AP1Rx(3)

/* A32-to-A64 mappings used by VGIC save/restore */

	return val; 				\

}

CPUIF_MAP(ICC_PMR, ICC_PMR_EL1)

CPUIF_MAP(ICC_AP0R0, ICC_AP0R0_EL1)

CPUIF_MAP(ICC_AP0R1, ICC_AP0R1_EL1)

CPUIF_MAP(ICC_AP0R2, ICC_AP0R2_EL1)

CPUIF_MAP(ICC_AP0R3, ICC_AP0R3_EL1)

CPUIF_MAP(ICC_AP1R0, ICC_AP1R0_EL1)

CPUIF_MAP(ICC_AP1R1, ICC_AP1R1_EL1)

CPUIF_MAP(ICC_AP1R2, ICC_AP1R2_EL1)

CPUIF_MAP(ICC_AP1R3, ICC_AP1R3_EL1)

CPUIF_MAP(ICH_HCR, ICH_HCR_EL2)

CPUIF_MAP(ICH_VTR, ICH_VTR_EL2)

CPUIF_MAP(ICH_MISR, ICH_MISR_EL2)

	return irqstat;

}

static inline void gic_write_pmr(u32 val)

{

	write_sysreg(val, ICC_PMR);

}

static inline void gic_write_ctlr(u32 val)

{

	write_sysreg(val, ICC_CTLR);

	return irqstat;

}

static inline void gic_write_pmr(u32 val)

{

	write_sysreg_s(val, SYS_ICC_PMR_EL1);

}

static inline void gic_write_ctlr(u32 val)

{

	write_sysreg_s(val, SYS_ICC_CTLR_EL1);