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Commit 71d91723 authored by Deepak Kumar's avatar Deepak Kumar
Browse files

msm: kgsl: Add support for A610 GPU 



Add GPU ID and required initial settings for
A610 GPU.

Change-Id: If1585f67bc9240bd90228f511bd81c11bf30fb39
Signed-off-by: default avatarDeepak Kumar <dkumar@codeaurora.org>
parent cfdc3af3

drivers/gpu/msm/adreno-gpulist.h

+24 −1
Original line number Diff line number Diff line
@@ -1101,7 +1101,7 @@ static const struct adreno_reglist a640_hwcg_regs[] = { 
	{A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},

};



/* These apply to a640, a680 and a612 */

/* These apply to a640, a680, a612 and a610 */

static const struct adreno_reglist a640_vbif_regs[] = {

	{A6XX_GBIF_QSB_SIDE0, 0x00071620},

	{A6XX_GBIF_QSB_SIDE1, 0x00071620},
@@ -1369,6 +1369,28 @@ static const struct adreno_a6xx_core adreno_gpu_core_a616 = { 
	.protected_regs = a630_protected_regs,

};



static const struct adreno_a6xx_core adreno_gpu_core_a610 = {

	{

		DEFINE_ADRENO_REV(ADRENO_REV_A610, 6, 1, 0, ANY_ID),

		.features = ADRENO_64BIT | ADRENO_CONTENT_PROTECTION |

			ADRENO_PREEMPTION,

		.gpudev = &adreno_a6xx_gpudev,

		.gmem_base = 0x100000,

		.gmem_size = (SZ_128K + SZ_4K),

		.busy_mask = 0xfffffffe,

		.bus_width = 32,

	},

	.prim_fifo_threshold = 0x00080000,

	.sqefw_name = "a630_sqe.fw",

	.zap_name = "a610_zap",

	.hwcg = a612_hwcg_regs,

	.hwcg_count = ARRAY_SIZE(a612_hwcg_regs),

	.vbif = a640_vbif_regs,

	.vbif_count = ARRAY_SIZE(a640_vbif_regs),

	.hang_detect_cycles = 0x3ffff,

	.protected_regs = a630_protected_regs,

};



static const struct adreno_gpu_core *adreno_gpulist[] = {

	&adreno_gpu_core_a306.base,

	&adreno_gpu_core_a306a.base,
@@ -1398,4 +1420,5 @@ static const struct adreno_gpu_core *adreno_gpulist[] = { 
	&adreno_gpu_core_a680.base,

	&adreno_gpu_core_a612.base,

	&adreno_gpu_core_a616.base,

	&adreno_gpu_core_a610.base,

};

drivers/gpu/msm/adreno.c

+4 −1
Original line number Diff line number Diff line
@@ -2244,10 +2244,13 @@ static inline bool adreno_try_soft_reset(struct kgsl_device *device, int fault) 
	 * needs a reset too) and also for below gpu

	 * A304: It can't do SMMU programming of any kind after a soft reset

	 * A612: IPC protocol between RGMU and CP will not restart after reset

	 * A610: An across chip issue with reset line in all 11nm chips,

	 * resulting in recommendation to not use soft reset

	 */



	if ((fault & ADRENO_IOMMU_PAGE_FAULT) || adreno_is_a304(adreno_dev) ||

			adreno_is_a612(adreno_dev))

			adreno_is_a612(adreno_dev) ||

			adreno_is_a610(adreno_dev))

		return false;



	return true;

drivers/gpu/msm/adreno.h

+2 −0
Original line number Diff line number Diff line
@@ -193,6 +193,7 @@ enum adreno_gpurev { 
	ADRENO_REV_A512 = 512,

	ADRENO_REV_A530 = 530,

	ADRENO_REV_A540 = 540,

	ADRENO_REV_A610 = 610,

	ADRENO_REV_A612 = 612,

	ADRENO_REV_A615 = 615,

	ADRENO_REV_A616 = 616,
@@ -1156,6 +1157,7 @@ static inline int adreno_is_a6xx(struct adreno_device *adreno_dev) 
			ADRENO_GPUREV(adreno_dev) < 700;

}



ADRENO_TARGET(a610, ADRENO_REV_A610)

ADRENO_TARGET(a612, ADRENO_REV_A612)

ADRENO_TARGET(a618, ADRENO_REV_A618)

ADRENO_TARGET(a620, ADRENO_REV_A620)

drivers/gpu/msm/adreno_a6xx.c

+37 −16
Original line number Diff line number Diff line
@@ -7,6 +7,7 @@ 
#include <linux/of.h>

#include <linux/of_fdt.h>

#include <soc/qcom/subsystem_restart.h>

#include <linux/clk/qcom.h>



#include "adreno.h"

#include "adreno_a6xx.h"
@@ -199,7 +200,7 @@ __get_rbbm_clock_cntl_on(struct adreno_device *adreno_dev) 
{

	if (adreno_is_a630(adreno_dev))

		return 0x8AA8AA02;

	else if (adreno_is_a612(adreno_dev))

	else if (adreno_is_a612(adreno_dev) || adreno_is_a610(adreno_dev))

		return 0xAAA8AA82;

	else

		return 0x8AA8AA82;
@@ -278,11 +279,12 @@ static void a6xx_hwcg_set(struct adreno_device *adreno_dev, bool on) 


	/*

	 * Disable SP clock before programming HWCG registers.

	 * A612 GPU is not having the GX power domain. Hence

	 * skip GMU_GX registers for A12.

	 * A612 and A610 GPU is not having the GX power domain.

	 * Hence skip GMU_GX registers for A12 and A610.

	 */



	if (gmu_core_isenabled(device) && !adreno_is_a612(adreno_dev))

	if (gmu_core_isenabled(device) && !adreno_is_a612(adreno_dev) &&

		!adreno_is_a610(adreno_dev))

		gmu_core_regrmw(device,

			A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 1, 0);
@@ -292,10 +294,11 @@ static void a6xx_hwcg_set(struct adreno_device *adreno_dev, bool on) 


	/*

	 * Enable SP clock after programming HWCG registers.

	 * A612 GPU is not having the GX power domain. Hence

	 * skip GMU_GX registers for A612.

	 * A612 and A610 GPU is not having the GX power domain.

	 * Hence skip GMU_GX registers for A612.

	 */

	if (gmu_core_isenabled(device) && !adreno_is_a612(adreno_dev))

	if (gmu_core_isenabled(device) && !adreno_is_a612(adreno_dev) &&

		!adreno_is_a610(adreno_dev))

		gmu_core_regrmw(device,

			A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 0, 1);
@@ -429,7 +432,7 @@ static void a6xx_start(struct adreno_device *adreno_dev) 
	if (ADRENO_GPUREV(adreno_dev) >= ADRENO_REV_A640) {

		kgsl_regwrite(device, A6XX_CP_ROQ_THRESHOLDS_2, 0x02000140);

		kgsl_regwrite(device, A6XX_CP_ROQ_THRESHOLDS_1, 0x8040362C);

	} else if (adreno_is_a612(adreno_dev)) {

	} else if (adreno_is_a612(adreno_dev) || adreno_is_a610(adreno_dev)) {

		kgsl_regwrite(device, A6XX_CP_ROQ_THRESHOLDS_2, 0x00800060);

		kgsl_regwrite(device, A6XX_CP_ROQ_THRESHOLDS_1, 0x40201b16);

	} else {
@@ -437,8 +440,8 @@ static void a6xx_start(struct adreno_device *adreno_dev) 
		kgsl_regwrite(device, A6XX_CP_ROQ_THRESHOLDS_1, 0x8040362C);

	}



	if (adreno_is_a612(adreno_dev)) {

		/* For A612 Mem pool size is reduced to 48 */

	if (adreno_is_a612(adreno_dev) || adreno_is_a610(adreno_dev)) {

		/* For A612 and A610 Mem pool size is reduced to 48 */

		kgsl_regwrite(device, A6XX_CP_MEM_POOL_SIZE, 48);

		kgsl_regwrite(device, A6XX_CP_MEM_POOL_DBG_ADDR, 47);

	} else {
@@ -853,9 +856,6 @@ static int a6xx_rb_start(struct adreno_device *adreno_dev) 
 */

static int a6xx_sptprac_enable(struct adreno_device *adreno_dev)

{

	if (adreno_is_a612(adreno_dev))

		return 0;



	return a6xx_gmu_sptprac_enable(adreno_dev);

}
@@ -865,9 +865,6 @@ static int a6xx_sptprac_enable(struct adreno_device *adreno_dev) 
 */

static void a6xx_sptprac_disable(struct adreno_device *adreno_dev)

{

	if (adreno_is_a612(adreno_dev))

		return;



	a6xx_gmu_sptprac_disable(adreno_dev);

}
@@ -2513,6 +2510,29 @@ static int a6xx_perfcounter_update(struct adreno_device *adreno_dev, 
	return 0;

}



static void a6xx_clk_set_options(struct adreno_device *adreno_dev,

	const char *name, struct clk *clk, bool on)

{

	if (!adreno_is_a610(adreno_dev))

		return;



	/* Handle clock settings for GFX PSCBCs */

	if (on) {

		if (!strcmp(name, "mem_iface_clk")) {

			clk_set_flags(clk, CLKFLAG_NORETAIN_PERIPH);

			clk_set_flags(clk, CLKFLAG_NORETAIN_MEM);

		} else if (!strcmp(name, "core_clk")) {

			clk_set_flags(clk, CLKFLAG_RETAIN_PERIPH);

			clk_set_flags(clk, CLKFLAG_RETAIN_MEM);

		}

	} else {

		if (!strcmp(name, "core_clk")) {

			clk_set_flags(clk, CLKFLAG_NORETAIN_PERIPH);

			clk_set_flags(clk, CLKFLAG_NORETAIN_MEM);

		}

	}

}



struct adreno_gpudev adreno_a6xx_gpudev = {

	.reg_offsets = &a6xx_reg_offsets,

	.start = a6xx_start,
@@ -2549,4 +2569,5 @@ struct adreno_gpudev adreno_a6xx_gpudev = { 
	.ccu_invalidate = a6xx_ccu_invalidate,

	.perfcounter_update = a6xx_perfcounter_update,

	.coresight = {&a6xx_coresight, &a6xx_coresight_cx},

	.clk_set_options = a6xx_clk_set_options,

};

drivers/gpu/msm/adreno_a6xx_snapshot.c

+11 −0
Original line number Diff line number Diff line
@@ -379,6 +379,13 @@ static const unsigned int a6xx_pre_crashdumper_registers[] = { 
	0x825, 0x825,

};



static const unsigned int a6xx_gmu_wrapper_registers[] = {

	/* GMU CX */

	0x1f840, 0x1f840, 0x1f844, 0x1f845, 0x1f887, 0x1f889,

	/* GMU AO*/

	0x23b0C, 0x23b0E, 0x23b15, 0x23b15,

};



enum a6xx_debugbus_id {

	A6XX_DBGBUS_CP           = 0x1,

	A6XX_DBGBUS_RBBM         = 0x2,
@@ -1763,6 +1770,10 @@ void a6xx_snapshot(struct adreno_device *adreno_dev, 
		adreno_snapshot_registers(device, snapshot,

			a6xx_rscc_snapshot_registers,

			ARRAY_SIZE(a6xx_rscc_snapshot_registers) / 2);

	} else if (adreno_is_a610(adreno_dev)) {

		adreno_snapshot_registers(device, snapshot,

			a6xx_gmu_wrapper_registers,

			ARRAY_SIZE(a6xx_gmu_wrapper_registers) / 2);

	}



	sptprac_on = gpudev->sptprac_is_on(adreno_dev);