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Commit 70eafad8 authored by Takashi Iwai's avatar Takashi Iwai
Browse files

ALSA: hda - Move SKL+ vendor specific register definitions to hda_register.h 



They may be used by both legacy and ASoC drivers.

Acked-by: default avatarVinod Koul <vinod.koul@intel.com>
Signed-off-by: default avatarTakashi Iwai <tiwai@suse.de>
parent 2c1f8138

include/sound/hda_register.h

+20 −2
Original line number Diff line number Diff line
@@ -106,8 +106,26 @@ enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 }; 
#define AZX_REG_HSW_EM4			0x100c

#define AZX_REG_HSW_EM5			0x1010



/* Skylake/Broxton display HD-A controller Extended Mode registers */

#define AZX_REG_SKL_EM4L		0x1040

/* Skylake/Broxton vendor-specific registers */

#define AZX_REG_VS_EM1			0x1000

#define AZX_REG_VS_INRC			0x1004

#define AZX_REG_VS_OUTRC		0x1008

#define AZX_REG_VS_FIFOTRK		0x100C

#define AZX_REG_VS_FIFOTRK2		0x1010

#define AZX_REG_VS_EM2			0x1030

#define AZX_REG_VS_EM3L			0x1038

#define AZX_REG_VS_EM3U			0x103C

#define AZX_REG_VS_EM4L			0x1040

#define AZX_REG_VS_EM4U			0x1044

#define AZX_REG_VS_LTRC			0x1048

#define AZX_REG_VS_D0I3C		0x104A

#define AZX_REG_VS_PCE			0x104B

#define AZX_REG_VS_L2MAGC		0x1050

#define AZX_REG_VS_L2LAHPT		0x1054

#define AZX_REG_VS_SDXDPIB_XBASE	0x1084

#define AZX_REG_VS_SDXDPIB_XINTERVAL	0x20

#define AZX_REG_VS_SDXEFIFOS_XBASE	0x1094

#define AZX_REG_VS_SDXEFIFOS_XINTERVAL	0x20



/* PCI space */

#define AZX_PCIREG_TCSEL		0x44

sound/pci/hda/hda_intel.c

+2 −2
Original line number Diff line number Diff line
@@ -534,9 +534,9 @@ static void bxt_reduce_dma_latency(struct azx *chip) 
{

	u32 val;



	val = azx_readl(chip, SKL_EM4L);

	val = azx_readl(chip, VS_EM4L);

	val &= (0x3 << 20);

	azx_writel(chip, SKL_EM4L, val);

	azx_writel(chip, VS_EM4L, val);

}



static void hda_intel_init_chip(struct azx *chip, bool full_reset)

sound/soc/intel/skylake/skl.h

+0 −21
Original line number Diff line number Diff line
@@ -27,27 +27,6 @@ 


#define SKL_SUSPEND_DELAY 2000



/* Vendor Specific Registers */

#define AZX_REG_VS_EM1			0x1000

#define AZX_REG_VS_INRC			0x1004

#define AZX_REG_VS_OUTRC		0x1008

#define AZX_REG_VS_FIFOTRK		0x100C

#define AZX_REG_VS_FIFOTRK2		0x1010

#define AZX_REG_VS_EM2			0x1030

#define AZX_REG_VS_EM3L			0x1038

#define AZX_REG_VS_EM3U			0x103C

#define AZX_REG_VS_EM4L			0x1040

#define AZX_REG_VS_EM4U			0x1044

#define AZX_REG_VS_LTRC			0x1048

#define AZX_REG_VS_D0I3C		0x104A

#define AZX_REG_VS_PCE			0x104B

#define AZX_REG_VS_L2MAGC		0x1050

#define AZX_REG_VS_L2LAHPT		0x1054

#define AZX_REG_VS_SDXDPIB_XBASE	0x1084

#define AZX_REG_VS_SDXDPIB_XINTERVAL	0x20

#define AZX_REG_VS_SDXEFIFOS_XBASE	0x1094

#define AZX_REG_VS_SDXEFIFOS_XINTERVAL	0x20



#define AZX_PCIREG_PGCTL		0x44

#define AZX_PGCTL_LSRMD_MASK		(1 << 4)

#define AZX_PCIREG_CGCTL		0x48