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Commit 70dd9d2f authored by Linus Walleij's avatar Linus Walleij Committed by Greg Kroah-Hartman
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coresight: document the bindings for the ATCLK



Put in a blurb in the device tree bindings indicating that
coresight blocks may have an optional ATCLK.

Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: default avatarMathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 9875cd9c
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+8 −5
Original line number Diff line number Diff line
@@ -21,11 +21,14 @@ its hardware characteristcs.
	* reg: physical base address and length of the register
	  set(s) of the component.

	* clocks: the clock associated to this component.

	* clock-names: the name of the clock as referenced by the code.
	  Since we are using the AMBA framework, the name should be
	  "apb_pclk".
	* clocks: the clocks associated to this component.

	* clock-names: the name of the clocks referenced by the code.
	  Since we are using the AMBA framework, the name of the clock
	  providing the interconnect should be "apb_pclk", and some
	  coresight blocks also have an additional clock "atclk", which
	  clocks the core of that coresight component. The latter clock
	  is optional.

	* port or ports: The representation of the component's port
	  layout using the generic DT graph presentation found in