Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 7061a118 authored by Priyanka Gujjula's avatar Priyanka Gujjula
Browse files

msm: vidc: Align buffer size calculators with num_vpp_pipes 



Buffer size calculators are dependent on pipe configuration
of the chipset. Ex: Kona has 4 pipes and lagoon has 1 pipe.
Hence aligning the buffer size calculators based on chipset
specific usage of pipes.

Change-Id: I8bb19efc4a80c7e17d9db3cf7d5f1151191b502e
Signed-off-by: default avatarPriyanka Gujjula <pgujjula@codeaurora.org>
parent 59f193a1

msm/vidc/msm_vidc_buffer_calculations.c

+99 −87
Original line number Diff line number Diff line
@@ -77,7 +77,6 @@ 


#define VENUS_DMA_ALIGNMENT BUFFER_ALIGNMENT_SIZE(256)



#define NUM_OF_VPP_PIPES 4

#define MAX_FE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE   64

#define MAX_FE_NBR_CTRL_LCU32_LINE_BUFFER_SIZE   64

#define MAX_FE_NBR_CTRL_LCU16_LINE_BUFFER_SIZE   64
@@ -141,10 +140,9 @@ 
#define SIZE_HW_PIC(sizePerBuf) \

	(NUM_HW_PIC_BUF * sizePerBuf)



#define H264_CABAC_HDR_RATIO_HD_TOT_NUM 1  /* 0.25 */

#define H264_CABAC_HDR_RATIO_HD_TOT_DEN 4

#define H264_CABAC_RES_RATIO_HD_TOT_NUM 3  /* 0.75 */

#define H264_CABAC_RES_RATIO_HD_TOT_DEN 4

#define H264_CABAC_HDR_RATIO_HD_TOT 1

#define H264_CABAC_RES_RATIO_HD_TOT 3



/*

 * some content need more bin buffer, but limit buffer

 * size for high resolution
@@ -198,10 +196,9 @@ 


#define SIZE_H265D_QP(width, height) SIZE_H264D_QP(width, height)



#define H265_CABAC_HDR_RATIO_HD_TOT_NUM 1

#define H265_CABAC_HDR_RATIO_HD_TOT_DEN 2

#define H265_CABAC_RES_RATIO_HD_TOT_NUM 1

#define H265_CABAC_RES_RATIO_HD_TOT_DEN 2

#define H265_CABAC_HDR_RATIO_HD_TOT 2

#define H265_CABAC_RES_RATIO_HD_TOT 2



/*

 * some content need more bin buffer, but limit buffer size

 * for high resolution
@@ -294,31 +291,36 @@ static inline u32 calculate_mpeg2d_scratch_size(struct msm_vidc_inst *inst, 
	u32 width, u32 height, bool is_interlaced);



static inline u32 calculate_enc_scratch_size(struct msm_vidc_inst *inst,

	u32 width, u32 height, u32 work_mode, u32 lcu_size);

	u32 width, u32 height, u32 work_mode, u32 lcu_size, u32 num_vpp_pipes);

static inline u32 calculate_h264e_scratch_size(struct msm_vidc_inst *inst,

	u32 width, u32 height, u32 work_mode);

	u32 width, u32 height, u32 work_mode, u32 num_vpp_pipes);

static inline u32 calculate_h265e_scratch_size(struct msm_vidc_inst *inst,

	u32 width, u32 height, u32 work_mode);

	u32 width, u32 height, u32 work_mode, u32 num_vpp_pipes);

static inline u32 calculate_vp8e_scratch_size(struct msm_vidc_inst *inst,

	u32 width, u32 height, u32 work_mode);

	u32 width, u32 height, u32 work_mode, u32 num_vpp_pipes);



static inline u32 calculate_h264d_scratch1_size(struct msm_vidc_inst *inst,

	u32 width, u32 height, u32 min_buf_count, bool split_mode_enabled);

	u32 width, u32 height, u32 min_buf_count, bool split_mode_enabled,

	u32 num_vpp_pipes);

static inline u32 calculate_h265d_scratch1_size(struct msm_vidc_inst *inst,

	u32 width, u32 height, u32 min_buf_count, bool split_mode_enabled);

	u32 width, u32 height, u32 min_buf_count, bool split_mode_enabled,

	u32 num_vpp_pipes);

static inline u32 calculate_vp8d_scratch1_size(struct msm_vidc_inst *inst,

	u32 width, u32 height, u32 min_buf_count, bool split_mode_enabled);

	u32 width, u32 height, u32 min_buf_count, bool split_mode_enabled,

	u32 num_vpp_pipes);

static inline u32 calculate_vp9d_scratch1_size(struct msm_vidc_inst *inst,

	u32 width, u32 height, u32 min_buf_count, bool split_mode_enabled);

	u32 width, u32 height, u32 min_buf_count, bool split_mode_enabled,

	u32 num_vpp_pipes);

static inline u32 calculate_mpeg2d_scratch1_size(struct msm_vidc_inst *inst,

	u32 width, u32 height, u32 min_buf_count, bool split_mode_enabled);

	u32 width, u32 height, u32 min_buf_count, bool split_mode_enabled,

	u32 num_vpp_pipes);



static inline u32 calculate_h264e_scratch1_size(struct msm_vidc_inst *inst,

	u32 width, u32 height, u32 num_ref, bool ten_bit);

	u32 width, u32 height, u32 num_ref, bool ten_bit, u32 num_vpp_pipes);

static inline u32 calculate_h265e_scratch1_size(struct msm_vidc_inst *inst,

	u32 width, u32 height, u32 num_ref, bool ten_bit);

	u32 width, u32 height, u32 num_ref, bool ten_bit, u32 num_vpp_pipes);

static inline u32 calculate_vp8e_scratch1_size(struct msm_vidc_inst *inst,

	u32 width, u32 height, u32 num_ref, bool ten_bit);

	u32 width, u32 height, u32 num_ref, bool ten_bit, u32 num_vpp_pipes);



static inline u32 calculate_enc_scratch2_size(struct msm_vidc_inst *inst,

	u32 width, u32 height, u32 num_ref, bool ten_bit);
@@ -385,14 +387,15 @@ static struct msm_vidc_enc_buff_size_calculators vp8e_calculators = { 
int msm_vidc_get_decoder_internal_buffer_sizes(struct msm_vidc_inst *inst)

{

	struct msm_vidc_dec_buff_size_calculators *dec_calculators;

	u32 width, height, i, out_min_count;

	u32 width, height, i, out_min_count, num_vpp_pipes;

	struct v4l2_format *f;



	if (!inst) {

	if (!inst || !inst->core || !inst->core->platform_data) {

		d_vpr_e("%s: Instance is null!", __func__);

		return -EINVAL;

	}



	num_vpp_pipes = inst->core->platform_data->num_vpp_pipes;

	f = &inst->fmts[INPUT_PORT].v4l2_fmt;

	switch (f->fmt.pix_mp.pixelformat) {

	case V4L2_PIX_FMT_H264:
@@ -442,7 +445,8 @@ int msm_vidc_get_decoder_internal_buffer_sizes(struct msm_vidc_inst *inst) 
			curr_req->buffer_size =

				dec_calculators->calculate_scratch1_size(

					inst, width, height, out_min_count,

					is_secondary_output_mode(inst));

					is_secondary_output_mode(inst),

					num_vpp_pipes);

			valid_buffer_type = true;

		} else if (curr_req->buffer_type ==

			HAL_BUFFER_INTERNAL_PERSIST_1) {
@@ -502,17 +506,18 @@ int msm_vidc_get_num_ref_frames(struct msm_vidc_inst *inst) 
int msm_vidc_get_encoder_internal_buffer_sizes(struct msm_vidc_inst *inst)

{

	struct msm_vidc_enc_buff_size_calculators *enc_calculators;

	u32 width, height, i, num_ref;

	u32 width, height, i, num_ref, num_vpp_pipes;

	bool is_tenbit = false;

	int num_bframes;

	struct v4l2_ctrl *bframe;

	struct v4l2_format *f;



	if (!inst) {

	if (!inst || !inst->core || !inst->core->platform_data) {

		d_vpr_e("%s: Instance is null!", __func__);

		return -EINVAL;

	}



	num_vpp_pipes = inst->core->platform_data->num_vpp_pipes;

	f = &inst->fmts[OUTPUT_PORT].v4l2_fmt;

	switch (f->fmt.pix_mp.pixelformat) {

	case V4L2_PIX_FMT_H264:
@@ -553,14 +558,15 @@ int msm_vidc_get_encoder_internal_buffer_sizes(struct msm_vidc_inst *inst) 
			curr_req->buffer_size =

				enc_calculators->calculate_scratch_size(

					inst, width, height,

					inst->clk_data.work_mode);

					inst->clk_data.work_mode,

					num_vpp_pipes);

			valid_buffer_type = true;

		} else  if (curr_req->buffer_type ==

			HAL_BUFFER_INTERNAL_SCRATCH_1) {

			curr_req->buffer_size =

				enc_calculators->calculate_scratch1_size(

					inst, width, height, num_ref,

					is_tenbit);

					is_tenbit, num_vpp_pipes);

			valid_buffer_type = true;

		} else if (curr_req->buffer_type ==

			HAL_BUFFER_INTERNAL_SCRATCH_2) {
@@ -1082,7 +1088,7 @@ u32 msm_vidc_calculate_enc_output_extra_size(struct msm_vidc_inst *inst) 
	return ALIGN(size, SZ_4K);

}



static inline u32 size_vpss_lb(u32 width, u32 height)

static inline u32 size_vpss_lb(u32 width, u32 height, u32 num_vpp_pipes)

{

	u32 vpss_4tap_top_buffer_size, vpss_div2_top_buffer_size;

	u32 vpss_4tap_left_buffer_size, vpss_div2_left_buffer_size;
@@ -1104,7 +1110,7 @@ static inline u32 size_vpss_lb(u32 width, u32 height) 
	opb_lb_wr_llb_uv_buffer_size = opb_lb_wr_llb_y_buffer_size =

		ALIGN((ALIGN(height, 16) / 2) *

			64, BUFFER_ALIGNMENT_SIZE(32));

	size = NUM_OF_VPP_PIPES * 2 * (vpss_4tap_top_buffer_size +

	size = num_vpp_pipes * 2 * (vpss_4tap_top_buffer_size +

		vpss_div2_top_buffer_size) +

		2 * (vpss_4tap_left_buffer_size +

		vpss_div2_left_buffer_size) +
@@ -1164,7 +1170,8 @@ static inline u32 size_h264d_vpp_cmd_buf(u32 height) 
		SIZE_H264D_VPP_CMD_PER_BUF;

}



static inline u32 hfi_iris2_h264d_non_comv_size(u32 width, u32 height)

static inline u32 hfi_iris2_h264d_non_comv_size(u32 width, u32 height,

	u32 num_vpp_pipes)

{

	u32 size;

	u32 size_bse, size_vpp;
@@ -1179,11 +1186,11 @@ static inline u32 hfi_iris2_h264d_non_comv_size(u32 width, u32 height) 
		ALIGN(SIZE_H264D_LB_FE_TOP_CTRL(width, height),

			VENUS_DMA_ALIGNMENT) +

		ALIGN(SIZE_H264D_LB_FE_LEFT_CTRL(width, height),

			VENUS_DMA_ALIGNMENT) * NUM_OF_VPP_PIPES +

			VENUS_DMA_ALIGNMENT) * num_vpp_pipes +

		ALIGN(SIZE_H264D_LB_SE_TOP_CTRL(width, height),

			VENUS_DMA_ALIGNMENT) +

		ALIGN(SIZE_H264D_LB_SE_LEFT_CTRL(width, height),

			VENUS_DMA_ALIGNMENT) * NUM_OF_VPP_PIPES +

			VENUS_DMA_ALIGNMENT) * num_vpp_pipes +

		ALIGN(SIZE_H264D_LB_PE_TOP_DATA(width, height),

			VENUS_DMA_ALIGNMENT) +

		ALIGN(SIZE_H264D_LB_VSP_TOP(width, height),
@@ -1206,10 +1213,8 @@ static inline u32 size_h264d_hw_bin_buffer(u32 width, u32 height) 
			((BIN_BUFFER_THRESHOLD * 3) >> 1) :

			((product * 3) >> 1);



	size_bin_hdr = size_yuv * H264_CABAC_HDR_RATIO_HD_TOT_NUM /

		H264_CABAC_HDR_RATIO_HD_TOT_DEN;

	size_bin_res = size_yuv * H264_CABAC_RES_RATIO_HD_TOT_NUM /

		H264_CABAC_RES_RATIO_HD_TOT_DEN;

	size_bin_hdr = size_yuv * H264_CABAC_HDR_RATIO_HD_TOT;

	size_bin_res = size_yuv * H264_CABAC_RES_RATIO_HD_TOT;

	size_bin_hdr = ALIGN(size_bin_hdr, VENUS_DMA_ALIGNMENT);

	size_bin_res = ALIGN(size_bin_res, VENUS_DMA_ALIGNMENT);

	size = size_bin_hdr + size_bin_res;
@@ -1223,12 +1228,10 @@ static inline u32 calculate_h264d_scratch_size(struct msm_vidc_inst *inst, 
	u32 aligned_height = ALIGN(height, BUFFER_ALIGNMENT_SIZE(16));

	u32 size = 0;



	if (!is_interlaced) {

	if (!is_interlaced)

		size = size_h264d_hw_bin_buffer(aligned_width, aligned_height);

		size = size * NUM_OF_VPP_PIPES;

	} else {

	else

		size = 0;

	}



	return size;

}
@@ -1275,7 +1278,8 @@ static inline u32 hfi_iris2_h265d_comv_size(u32 width, u32 height, 
	return size;

}



static inline u32 hfi_iris2_h265d_non_comv_size(u32 width, u32 height)

static inline u32 hfi_iris2_h265d_non_comv_size(u32 width, u32 height,

	u32 num_vpp_pipes)

{

	u32 size_bse, size_vpp;

	u32 size = 0;
@@ -1295,9 +1299,9 @@ static inline u32 hfi_iris2_h265d_non_comv_size(u32 width, u32 height) 
		ALIGN(SIZE_H265D_LB_FE_TOP_CTRL(width, height),

			VENUS_DMA_ALIGNMENT) +

		ALIGN(SIZE_H265D_LB_FE_LEFT_CTRL(width, height),

			VENUS_DMA_ALIGNMENT) * NUM_OF_VPP_PIPES +

			VENUS_DMA_ALIGNMENT) * num_vpp_pipes +

		ALIGN(SIZE_H265D_LB_SE_LEFT_CTRL(width, height),

			VENUS_DMA_ALIGNMENT) * NUM_OF_VPP_PIPES +

			VENUS_DMA_ALIGNMENT) * num_vpp_pipes +

		ALIGN(SIZE_H265D_LB_SE_TOP_CTRL(width, height),

			VENUS_DMA_ALIGNMENT) +

		ALIGN(SIZE_H265D_LB_PE_TOP_DATA(width, height),
@@ -1305,7 +1309,7 @@ static inline u32 hfi_iris2_h265d_non_comv_size(u32 width, u32 height) 
		ALIGN(SIZE_H265D_LB_VSP_TOP(width, height),

			VENUS_DMA_ALIGNMENT) +

		ALIGN(SIZE_H265D_LB_VSP_LEFT(width, height),

			VENUS_DMA_ALIGNMENT) * NUM_OF_VPP_PIPES +

			VENUS_DMA_ALIGNMENT) * num_vpp_pipes +

		ALIGN(SIZE_H265D_LB_RECON_DMA_METADATA_WR(width, height),

			VENUS_DMA_ALIGNMENT) * 4 +

		ALIGN(SIZE_H265D_QP(width, height), VENUS_DMA_ALIGNMENT);
@@ -1323,10 +1327,8 @@ static inline u32 size_h265d_hw_bin_buffer(u32 width, u32 height) 
	size_yuv = (product <= BIN_BUFFER_THRESHOLD) ?

		((BIN_BUFFER_THRESHOLD * 3) >> 1) :

		((product * 3) >> 1);

	size_bin_hdr = size_yuv * H265_CABAC_HDR_RATIO_HD_TOT_NUM /

		H265_CABAC_HDR_RATIO_HD_TOT_DEN;

	size_bin_res = size_yuv * H265_CABAC_RES_RATIO_HD_TOT_NUM /

		H265_CABAC_RES_RATIO_HD_TOT_DEN;

	size_bin_hdr = size_yuv * H265_CABAC_HDR_RATIO_HD_TOT;

	size_bin_res = size_yuv * H265_CABAC_RES_RATIO_HD_TOT;

	size_bin_hdr = ALIGN(size_bin_hdr, VENUS_DMA_ALIGNMENT);

	size_bin_res = ALIGN(size_bin_res, VENUS_DMA_ALIGNMENT);

	size = size_bin_hdr + size_bin_res;
@@ -1341,13 +1343,10 @@ static inline u32 calculate_h265d_scratch_size(struct msm_vidc_inst *inst, 
	u32 aligned_height = ALIGN(height, BUFFER_ALIGNMENT_SIZE(16));

	u32 size = 0;



	if (!is_interlaced) {

	if (!is_interlaced)

		size = size_h265d_hw_bin_buffer(aligned_width, aligned_height);

		size = size * NUM_OF_VPP_PIPES;

	} else {

	else

		size = 0;

	}



	return size;

}
@@ -1389,7 +1388,7 @@ static inline u32 calculate_mpeg2d_scratch_size(struct msm_vidc_inst *inst, 
}



static inline u32 calculate_enc_scratch_size(struct msm_vidc_inst *inst,

	u32 width, u32 height, u32 work_mode, u32 lcu_size)

	u32 width, u32 height, u32 work_mode, u32 lcu_size, u32 num_vpp_pipes)

{

	u32 aligned_width, aligned_height, bitstream_size;

	u32 total_bitbin_buffers = 0, size_singlePipe, bitbin_size = 0;
@@ -1409,7 +1408,10 @@ static inline u32 calculate_enc_scratch_size(struct msm_vidc_inst *inst, 
		bitstream_size = aligned_width * aligned_height * 3;

		bitbin_size = ALIGN(bitstream_size, VENUS_DMA_ALIGNMENT);

	}

	if (num_vpp_pipes > 2)

		size_singlePipe = bitbin_size / 2;

	else

		size_singlePipe = bitbin_size;

	if (inst->rc_type == RATE_CONTROL_LOSSLESS)

		size_singlePipe <<= 1;

	size_singlePipe = ALIGN(size_singlePipe, VENUS_DMA_ALIGNMENT);
@@ -1418,7 +1420,7 @@ static inline u32 calculate_enc_scratch_size(struct msm_vidc_inst *inst, 
	padded_bin_size = ALIGN(size_singlePipe, VENUS_DMA_ALIGNMENT);

	size_singlePipe = sao_bin_buffer_size + padded_bin_size;

	size_singlePipe = ALIGN(size_singlePipe, VENUS_DMA_ALIGNMENT);

	bitbin_size = size_singlePipe * NUM_OF_VPP_PIPES;

	bitbin_size = size_singlePipe * num_vpp_pipes;

	size = ALIGN(bitbin_size, VENUS_DMA_ALIGNMENT) * total_bitbin_buffers

			+ 512;
@@ -1426,50 +1428,56 @@ static inline u32 calculate_enc_scratch_size(struct msm_vidc_inst *inst, 
}



static inline u32 calculate_h264e_scratch_size(struct msm_vidc_inst *inst,

	u32 width, u32 height, u32 work_mode)

	u32 width, u32 height, u32 work_mode, u32 num_vpp_pipes)

{

	return calculate_enc_scratch_size(inst, width, height, work_mode, 16);

	return calculate_enc_scratch_size(inst, width, height, work_mode, 16,

		num_vpp_pipes);

}



static inline u32 calculate_h265e_scratch_size(struct msm_vidc_inst *inst,

	u32 width, u32 height, u32 work_mode)

	u32 width, u32 height, u32 work_mode, u32 num_vpp_pipes)

{

	return calculate_enc_scratch_size(inst, width, height, work_mode, 32);

	return calculate_enc_scratch_size(inst, width, height, work_mode, 32,

		num_vpp_pipes);

}



static inline u32 calculate_vp8e_scratch_size(struct msm_vidc_inst *inst,

	u32 width, u32 height, u32 work_mode)

	u32 width, u32 height, u32 work_mode, u32 num_vpp_pipes)

{

	return calculate_enc_scratch_size(inst, width, height, work_mode, 16);

	return calculate_enc_scratch_size(inst, width, height, work_mode, 16,

		num_vpp_pipes);

}



static inline u32 calculate_h264d_scratch1_size(struct msm_vidc_inst *inst,

	u32 width, u32 height, u32 min_buf_count, bool split_mode_enabled)

	u32 width, u32 height, u32 min_buf_count, bool split_mode_enabled,

	u32 num_vpp_pipes)

{

	u32 co_mv_size = 0, nonco_mv_size = 0;

	u32 vpss_lb_size = 0;

	u32 size = 0;



	co_mv_size = hfi_iris2_h264d_comv_size(width, height, min_buf_count);

	nonco_mv_size = hfi_iris2_h264d_non_comv_size(width, height);

	nonco_mv_size = hfi_iris2_h264d_non_comv_size(width, height,

			num_vpp_pipes);

	if (split_mode_enabled)

		vpss_lb_size = size_vpss_lb(width, height);



		vpss_lb_size = size_vpss_lb(width, height, num_vpp_pipes);

	size = co_mv_size + nonco_mv_size + vpss_lb_size;

	return size;

}



static inline u32 calculate_h265d_scratch1_size(struct msm_vidc_inst *inst,

	u32 width, u32 height, u32 min_buf_count, bool split_mode_enabled)

	u32 width, u32 height, u32 min_buf_count, bool split_mode_enabled,

	u32 num_vpp_pipes)

{

	u32 co_mv_size = 0, nonco_mv_size = 0;

	u32 vpss_lb_size = 0;

	u32 size = 0;



	co_mv_size = hfi_iris2_h265d_comv_size(width, height, min_buf_count);

	nonco_mv_size = hfi_iris2_h265d_non_comv_size(width, height);

	nonco_mv_size =

		hfi_iris2_h265d_non_comv_size(width, height, num_vpp_pipes);

	if (split_mode_enabled)

		vpss_lb_size = size_vpss_lb(width, height);

		vpss_lb_size = size_vpss_lb(width, height, num_vpp_pipes);



	size = co_mv_size + nonco_mv_size + vpss_lb_size +

			HDR10_HIST_EXTRADATA_SIZE;
@@ -1483,16 +1491,17 @@ static inline u32 hfi_iris2_vp8d_comv_size(u32 width, u32 height, 
}



static inline u32 calculate_vp8d_scratch1_size(struct msm_vidc_inst *inst,

	u32 width, u32 height, u32 min_buf_count, bool split_mode_enabled)

	u32 width, u32 height, u32 min_buf_count, bool split_mode_enabled,

	u32 num_vpp_pipes)

{

	u32 vpss_lb_size = 0;

	u32 size = 0;



	size = hfi_iris2_vp8d_comv_size(width, height, 0);

	size += ALIGN(SIZE_VPXD_LB_FE_LEFT_CTRL(width, height),

			VENUS_DMA_ALIGNMENT) * NUM_OF_VPP_PIPES +

			VENUS_DMA_ALIGNMENT) * num_vpp_pipes +

		ALIGN(SIZE_VPXD_LB_SE_LEFT_CTRL(width, height),

			VENUS_DMA_ALIGNMENT) * NUM_OF_VPP_PIPES +

			VENUS_DMA_ALIGNMENT) * num_vpp_pipes +

		ALIGN(SIZE_VP8D_LB_VSP_TOP(width, height),

			VENUS_DMA_ALIGNMENT) +

		ALIGN(SIZE_VPXD_LB_FE_TOP_CTRL(width, height),
@@ -1506,22 +1515,23 @@ static inline u32 calculate_vp8d_scratch1_size(struct msm_vidc_inst *inst, 
		ALIGN(SIZE_VP8D_LB_FE_TOP_DATA(width, height),

			VENUS_DMA_ALIGNMENT);

	if (split_mode_enabled)

		vpss_lb_size = size_vpss_lb(width, height);

		vpss_lb_size = size_vpss_lb(width, height, num_vpp_pipes);



	size += vpss_lb_size;

	return size;

}



static inline u32 calculate_vp9d_scratch1_size(struct msm_vidc_inst *inst,

	u32 width, u32 height, u32 min_buf_count, bool split_mode_enabled)

	u32 width, u32 height, u32 min_buf_count, bool split_mode_enabled,

	u32 num_vpp_pipes)

{

	u32 vpss_lb_size = 0;

	u32 size = 0;



	size = ALIGN(SIZE_VPXD_LB_FE_LEFT_CTRL(width, height),

			VENUS_DMA_ALIGNMENT) * NUM_OF_VPP_PIPES +

			VENUS_DMA_ALIGNMENT) * num_vpp_pipes +

		ALIGN(SIZE_VPXD_LB_SE_LEFT_CTRL(width, height),

			VENUS_DMA_ALIGNMENT) * NUM_OF_VPP_PIPES +

			VENUS_DMA_ALIGNMENT) * num_vpp_pipes +

		ALIGN(SIZE_VP9D_LB_VSP_TOP(width, height),

			VENUS_DMA_ALIGNMENT) +

		ALIGN(SIZE_VPXD_LB_FE_TOP_CTRL(width, height),
@@ -1535,22 +1545,23 @@ static inline u32 calculate_vp9d_scratch1_size(struct msm_vidc_inst *inst, 
		ALIGN(SIZE_VP9D_LB_FE_TOP_DATA(width, height),

			VENUS_DMA_ALIGNMENT);

	if (split_mode_enabled)

		vpss_lb_size = size_vpss_lb(width, height);

		vpss_lb_size = size_vpss_lb(width, height, num_vpp_pipes);



	size += vpss_lb_size + HDR10_HIST_EXTRADATA_SIZE;

	return size;

}



static inline u32 calculate_mpeg2d_scratch1_size(struct msm_vidc_inst *inst,

	u32 width, u32 height, u32 min_buf_count, bool split_mode_enabled)

	u32 width, u32 height, u32 min_buf_count, bool split_mode_enabled,

	u32 num_vpp_pipes)

{

	u32 vpss_lb_size = 0;

	u32 size = 0;



	size = ALIGN(SIZE_VPXD_LB_FE_LEFT_CTRL(width, height),

			VENUS_DMA_ALIGNMENT) * NUM_OF_VPP_PIPES +

			VENUS_DMA_ALIGNMENT) * num_vpp_pipes +

		ALIGN(SIZE_VPXD_LB_SE_LEFT_CTRL(width, height),

			VENUS_DMA_ALIGNMENT) * NUM_OF_VPP_PIPES +

			VENUS_DMA_ALIGNMENT) * num_vpp_pipes +

		ALIGN(SIZE_VP8D_LB_VSP_TOP(width, height),

			VENUS_DMA_ALIGNMENT) +

		ALIGN(SIZE_VPXD_LB_FE_TOP_CTRL(width, height),
@@ -1564,7 +1575,7 @@ static inline u32 calculate_mpeg2d_scratch1_size(struct msm_vidc_inst *inst, 
		ALIGN(SIZE_VP8D_LB_FE_TOP_DATA(width, height),

			VENUS_DMA_ALIGNMENT);

	if (split_mode_enabled)

		vpss_lb_size = size_vpss_lb(width, height);

		vpss_lb_size = size_vpss_lb(width, height, num_vpp_pipes);



	size += vpss_lb_size;

	return size;
@@ -1720,22 +1731,23 @@ static inline u32 calculate_enc_scratch1_size(struct msm_vidc_inst *inst, 
}



static inline u32 calculate_h264e_scratch1_size(struct msm_vidc_inst *inst,

	u32 width, u32 height, u32 num_ref, bool ten_bit)

	u32 width, u32 height, u32 num_ref, bool ten_bit, u32 num_vpp_pipes)

{

	return calculate_enc_scratch1_size(inst, width, height, 16,

		num_ref, ten_bit, NUM_OF_VPP_PIPES, false);

		num_ref, ten_bit, num_vpp_pipes, false);

}



static inline u32 calculate_h265e_scratch1_size(struct msm_vidc_inst *inst,

	u32 width, u32 height, u32 num_ref, bool ten_bit)

	u32 width, u32 height, u32 num_ref, bool ten_bit, u32 num_vpp_pipes)

{

	return calculate_enc_scratch1_size(inst, width, height, 32,

		num_ref, ten_bit, NUM_OF_VPP_PIPES, true);

		num_ref, ten_bit, num_vpp_pipes, true);

}



static inline u32 calculate_vp8e_scratch1_size(struct msm_vidc_inst *inst,

	u32 width, u32 height, u32 num_ref, bool ten_bit)

	u32 width, u32 height, u32 num_ref, bool ten_bit, u32 num_vpp_pipes)

{

	(void)num_vpp_pipes;

	return calculate_enc_scratch1_size(inst, width, height, 16,

		num_ref, ten_bit, 1, false);

}

msm/vidc/msm_vidc_buffer_calculations.h

+6 −4
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0-only */

/*

 * Copyright (c) 2019, The Linux Foundation. All rights reserved.

 * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.

 */



#ifndef __H_MSM_VIDC_BUFFER_MEM_DEFS_H__
@@ -14,15 +14,17 @@ struct msm_vidc_dec_buff_size_calculators { 
	u32 (*calculate_scratch_size)(struct msm_vidc_inst *inst, u32 width,

		u32 height, bool is_interlaced);

	u32 (*calculate_scratch1_size)(struct msm_vidc_inst *inst, u32 width,

		u32 height, u32 min_buf_count, bool split_mode_enabled);

		u32 height, u32 min_buf_count, bool split_mode_enabled,

		u32 num_vpp_pipes);

	u32 (*calculate_persist1_size)(void);

};



struct msm_vidc_enc_buff_size_calculators {

	u32 (*calculate_scratch_size)(struct msm_vidc_inst *inst, u32 width,

		u32 height, u32 work_mode);

		u32 height, u32 work_mode, u32 num_vpp_pipes);

	u32 (*calculate_scratch1_size)(struct msm_vidc_inst *inst,

		u32 width, u32 height, u32 num_ref, bool ten_bit);

		u32 width, u32 height, u32 num_ref, bool ten_bit,

		u32 num_vpp_pipes);

	u32 (*calculate_scratch2_size)(struct msm_vidc_inst *inst,

		u32 width, u32 height, u32 num_ref, bool ten_bit);

	u32 (*calculate_persist_size)(void);

msm/vidc/msm_vidc_internal.h

+1 −0
Original line number Diff line number Diff line
@@ -304,6 +304,7 @@ struct msm_vidc_platform_data { 
	unsigned int efuse_data_length;

	unsigned int sku_version;

	uint32_t vpu_ver;

	uint32_t num_vpp_pipes;

	struct msm_vidc_ubwc_config_data *ubwc_config;

};

msm/vidc/msm_vidc_platform.c

+9 −0
Original line number Diff line number Diff line
@@ -1677,6 +1677,7 @@ static struct msm_vidc_platform_data default_data = { 
	.efuse_data_length = 0,

	.sku_version = 0,

	.vpu_ver = VPU_VERSION_IRIS2,

	.num_vpp_pipes = 0x4,

	.ubwc_config = 0x0,

};
@@ -1692,6 +1693,7 @@ static struct msm_vidc_platform_data lito_data = { 
	.efuse_data_length = ARRAY_SIZE(lito_efuse_data),

	.sku_version = 0,

	.vpu_ver = VPU_VERSION_IRIS1,

	.num_vpp_pipes = 0x2,

	.ubwc_config = 0x0,

	.codecs = default_codecs,

	.codecs_count = ARRAY_SIZE(default_codecs),
@@ -1711,6 +1713,7 @@ static struct msm_vidc_platform_data kona_data = { 
	.efuse_data_length = 0,

	.sku_version = 0,

	.vpu_ver = VPU_VERSION_IRIS2,

	.num_vpp_pipes = 0x4,

	.ubwc_config = kona_ubwc_data,

	.codecs = default_codecs,

	.codecs_count = ARRAY_SIZE(default_codecs),
@@ -1730,6 +1733,7 @@ static struct msm_vidc_platform_data lagoon_data = { 
	.efuse_data_length = ARRAY_SIZE(lagoon_efuse_data),

	.sku_version = 0,

	.vpu_ver = VPU_VERSION_IRIS2_1,

	.num_vpp_pipes = 0x1,

	.ubwc_config = 0x0,

	.codecs = lagoon_codecs,

	.codecs_count = ARRAY_SIZE(lagoon_codecs),
@@ -1749,6 +1753,7 @@ static struct msm_vidc_platform_data sm6150_data = { 
	.efuse_data_length = 0,

	.sku_version = 0,

	.vpu_ver = VPU_VERSION_AR50,

	.num_vpp_pipes = 0x1,

	.ubwc_config = 0x0,

};
@@ -1764,6 +1769,7 @@ static struct msm_vidc_platform_data bengal_data = { 
	.efuse_data_length = 0,

	.sku_version = 0,

	.vpu_ver = VPU_VERSION_AR50_LITE,

	.num_vpp_pipes = 0x1,

	.ubwc_config = 0x0,

	.codecs = bengal_codecs,

	.codecs_count = ARRAY_SIZE(bengal_codecs),
@@ -1783,6 +1789,7 @@ static struct msm_vidc_platform_data sm8150_data = { 
	.efuse_data_length = 0,

	.sku_version = 0,

	.vpu_ver = VPU_VERSION_IRIS1,

	.num_vpp_pipes = 0x2,

	.ubwc_config = 0x0,

};
@@ -1798,6 +1805,7 @@ static struct msm_vidc_platform_data sdm845_data = { 
	.efuse_data_length = 0,

	.sku_version = 0,

	.vpu_ver = VPU_VERSION_AR50,

	.num_vpp_pipes = 0x1,

	.ubwc_config = 0x0,

};
@@ -1813,6 +1821,7 @@ static struct msm_vidc_platform_data sdm670_data = { 
	.efuse_data_length = ARRAY_SIZE(sdm670_efuse_data),

	.sku_version = 0,

	.vpu_ver = VPU_VERSION_AR50,

	.num_vpp_pipes = 0x1,

	.ubwc_config = 0x0,

};