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Commit 705b3bd1 authored by Taniya Das's avatar Taniya Das Committed by Gerrit - the friendly Code Review server
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clk: qcom: clk-alpha-pll: Add support for FSM legacy mode 



The Lucid PLL could require the FSM legacy mode bit to be set for the
PLL to be operational, thus add support and set the same when the flag
is set.

While at it also update the Zonda disable function to remove the
additional offset usage.

Change-Id: I3ed4b6c38a1769c5021f17e0115215eab615ab62
Signed-off-by: default avatarTaniya Das <tdas@codeaurora.org>
parent e7babae0

drivers/clk/qcom/clk-alpha-pll.c

+7 −3
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0

/*

 * Copyright (c) 2015, 2018-2020, The Linux Foundation. All rights reserved.

 * Copyright (c) 2015, 2018-2021, The Linux Foundation. All rights reserved.

 */



#include <linux/kernel.h>
@@ -30,6 +30,7 @@ 
#define PLL_VOTE_FSM_RESET	BIT(21)

#define PLL_UPDATE		BIT(22)

#define PLL_UPDATE_BYPASS	BIT(23)

#define PLL_FSM_LEGACY_MODE	BIT(24)

#define PLL_ALPHA_EN		BIT(24)

#define PLL_OFFLINE_ACK		BIT(28)

#define ALPHA_PLL_ACK_LATCH	BIT(29)
@@ -1265,10 +1266,10 @@ static int clk_zonda_pll_enable(struct clk_hw *hw) 
static void clk_zonda_pll_disable(struct clk_hw *hw)

{

	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);

	u32 val, mask, off = pll->offset;

	u32 val, mask;

	int ret;



	ret = regmap_read(pll->clkr.regmap, off + PLL_MODE(pll), &val);

	ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);

	if (ret)

		return;
@@ -2076,6 +2077,9 @@ void clk_lucid_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 
				 PLL_UPDATE_BYPASS,

				 PLL_UPDATE_BYPASS);



	if (pll->flags & SUPPORTS_FSM_LEGACY_MODE)

		regmap_update_bits(regmap, PLL_MODE(pll), PLL_FSM_LEGACY_MODE,

						PLL_FSM_LEGACY_MODE);

	/* Disable PLL output */

	regmap_update_bits(regmap, PLL_MODE(pll),

					PLL_OUTCTRL, 0);

drivers/clk/qcom/clk-alpha-pll.h

+2 −1
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0 */

/* Copyright (c) 2015, 2018-2020, The Linux Foundation. All rights reserved. */

/* Copyright (c) 2015, 2018-2021, The Linux Foundation. All rights reserved. */



#ifndef __QCOM_CLK_ALPHA_PLL_H__

#define __QCOM_CLK_ALPHA_PLL_H__
@@ -91,6 +91,7 @@ struct clk_alpha_pll { 
#define SUPPORTS_SLEW		BIT(4)

	/* Associated with soft_vote for multiple PLL software instances */

#define SUPPORTS_FSM_VOTE	BIT(5)

#define SUPPORTS_FSM_LEGACY_MODE BIT(6)

	u8 flags;



	struct clk_regmap clkr;