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Commit 6fd45cb8 authored by Matt Carlson's avatar Matt Carlson Committed by David S. Miller
Browse files

tg3: Clarify semantics of TG3_IRQ_MAX_VECS 



TG3_IRQ_MAX_VECS should be seen as the maximum number of vectors that
any device could be expected to use.  tp->irq_max represents the maximum
number of vectors the current device can use.  This patch clarifies the
semantics of the code to match the above description.

Reviewed-by: default avatarBenjamin Li <benli@broadcom.com>
Reviewed-by: default avatarMichael Chan <mchan@broadcom.com>
Signed-off-by: default avatarMatt Carlson <mcarlson@broadcom.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 2e9f7a74

drivers/net/tg3.c

+3 −3
Original line number Diff line number Diff line
@@ -7564,7 +7564,7 @@ static void tg3_rings_reset(struct tg3 *tp) 


	/* Zero mailbox registers. */

	if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) {

		for (i = 1; i < TG3_IRQ_MAX_VECS; i++) {

		for (i = 1; i < tp->irq_max; i++) {

			tp->napi[i].tx_prod = 0;

			tp->napi[i].tx_cons = 0;

			if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
@@ -9886,7 +9886,7 @@ static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *e 
		tp->rx_pending = 63;

	tp->rx_jumbo_pending = ering->rx_jumbo_pending;



	for (i = 0; i < TG3_IRQ_MAX_VECS; i++)

	for (i = 0; i < tp->irq_max; i++)

		tp->napi[i].tx_pending = ering->tx_pending;



	if (netif_running(dev)) {
@@ -14598,7 +14598,7 @@ static int __devinit tg3_init_one(struct pci_dev *pdev, 
	intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;

	rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;

	sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;

	for (i = 0; i < TG3_IRQ_MAX_VECS; i++) {

	for (i = 0; i < tp->irq_max; i++) {

		struct tg3_napi *tnapi = &tp->napi[i];



		tnapi->tp = tp;

drivers/net/tg3.h

+2 −1
Original line number Diff line number Diff line
@@ -2659,7 +2659,8 @@ struct tg3_rx_prodring_set { 
	dma_addr_t			rx_jmb_mapping;

};



#define TG3_IRQ_MAX_VECS 5

#define TG3_IRQ_MAX_VECS_RSS		5

#define TG3_IRQ_MAX_VECS		TG3_IRQ_MAX_VECS_RSS



struct tg3_napi {

	struct napi_struct		napi	____cacheline_aligned;