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Commit 6fd16ce5 authored by Michael Cree's avatar Michael Cree Committed by Matt Turner
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alpha: Implement CPU vulnerabilities sysfs functions.



Implement the CPU vulnerabilty show functions for meltdown, spectre_v1
and spectre_v2 on Alpha.

Tests on XP1000 (EV67/667MHz) and ES45 (EV68CB/1.25GHz) show them
to be vulnerable to Meltdown and Spectre V1.  In the case of
Meltdown I saw a 1 to 2% success rate in reading bytes on the
XP1000 and 50 to 60% success rate on the ES45. (This compares to
99.97% success reported for Intel CPUs.)  Report EV6 and later
CPUs as vulnerable.

Tests on PWS600au (EV56/600MHz) for Spectre V1 attack were
unsuccessful (though I did not try particularly hard) so mark EV4
through to EV56 as not vulnerable.

Signed-off-by: default avatarMichael Cree <mcree@orcon.net.nz>
Signed-off-by: default avatarMatt Turner <mattst88@gmail.com>
parent 54f16b19
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+1 −0
Original line number Original line Diff line number Diff line
@@ -18,6 +18,7 @@ config ALPHA
	select ARCH_HAVE_NMI_SAFE_CMPXCHG
	select ARCH_HAVE_NMI_SAFE_CMPXCHG
	select AUDIT_ARCH
	select AUDIT_ARCH
	select GENERIC_CLOCKEVENTS
	select GENERIC_CLOCKEVENTS
	select GENERIC_CPU_VULNERABILITIES
	select GENERIC_SMP_IDLE_THREAD
	select GENERIC_SMP_IDLE_THREAD
	select GENERIC_STRNCPY_FROM_USER
	select GENERIC_STRNCPY_FROM_USER
	select GENERIC_STRNLEN_USER
	select GENERIC_STRNLEN_USER
+1 −1
Original line number Original line Diff line number Diff line
@@ -9,7 +9,7 @@ ccflags-y := -Wno-sign-compare


obj-y    := entry.o traps.o process.o osf_sys.o irq.o \
obj-y    := entry.o traps.o process.o osf_sys.o irq.o \
	    irq_alpha.o signal.o setup.o ptrace.o time.o \
	    irq_alpha.o signal.o setup.o ptrace.o time.o \
	    systbls.o err_common.o io.o
	    systbls.o err_common.o io.o bugs.o


obj-$(CONFIG_VGA_HOSE)	+= console.o
obj-$(CONFIG_VGA_HOSE)	+= console.o
obj-$(CONFIG_SMP)	+= smp.o
obj-$(CONFIG_SMP)	+= smp.o
+45 −0
Original line number Original line Diff line number Diff line

#include <asm/hwrpb.h>
#include <linux/device.h>


#ifdef CONFIG_SYSFS

static int cpu_is_ev6_or_later(void)
{
	struct percpu_struct *cpu;
        unsigned long cputype;

        cpu = (struct percpu_struct *)((char *)hwrpb + hwrpb->processor_offset);
        cputype = cpu->type & 0xffffffff;
        /* Include all of EV6, EV67, EV68, EV7, EV79 and EV69. */
        return (cputype == EV6_CPU) || ((cputype >= EV67_CPU) && (cputype <= EV69_CPU));
}

ssize_t cpu_show_meltdown(struct device *dev,
			  struct device_attribute *attr, char *buf)
{
	if (cpu_is_ev6_or_later())
		return sprintf(buf, "Vulnerable\n");
	else
		return sprintf(buf, "Not affected\n");
}

ssize_t cpu_show_spectre_v1(struct device *dev,
                            struct device_attribute *attr, char *buf)
{
	if (cpu_is_ev6_or_later())
		return sprintf(buf, "Vulnerable\n");
	else
		return sprintf(buf, "Not affected\n");
}

ssize_t cpu_show_spectre_v2(struct device *dev,
			    struct device_attribute *attr, char *buf)
{
	if (cpu_is_ev6_or_later())
		return sprintf(buf, "Vulnerable\n");
	else
		return sprintf(buf, "Not affected\n");
}
#endif