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Commit 6fd06660 authored by Daniel Borkmann's avatar Daniel Borkmann
Browse files

Merge branch 'bpf-arm-jit-improvements' 



Russell King says:

====================
This series improves the ARM BPF JIT compiler by:

- enumerating the stack layout rather than using constants that happen
  to be multiples of four
- rejig the BPF "register" accesses to use negative numbers instead of
  positive, which could be confused with register numbers in the bpf2a32
  array.
- since we maintain the ARM FP register as a pointer to the top of our
  scratch space (or, with frame pointers enabled, a valid ARM frame
  pointer register), we can access our scratch space using FP, which is
  constant across all BPF programs, including tail-called programs.
- use immediate forms of ARM instructions where possible, rather than
  first loading the immediate into an ARM register.
- use load-with-shift instruction rather than seperate shift instruction
  followed by load
- avoid reloading index and array in the tail-call code
- use double-word load/store instructions where available

Version 2:

- Fix ARMv5 test pointed out by Olof
- Fix build error found by 0-day (adding an additional patch)
====================

Signed-off-by: default avatarDaniel Borkmann <daniel@iogearbox.net>
parents b103cbe0 8c9602d3

arch/arm/net/bpf_jit_32.c

+523 −459

File changed.

Preview size limit exceeded, changes collapsed.

arch/arm/net/bpf_jit_32.h

+20 −22
Original line number Diff line number Diff line
@@ -77,11 +77,14 @@ 
#define ARM_INST_EOR_R		0x00200000

#define ARM_INST_EOR_I		0x02200000



#define ARM_INST_LDRB_I		0x05d00000

#define ARM_INST_LDST__U	0x00800000

#define ARM_INST_LDST__IMM12	0x00000fff

#define ARM_INST_LDRB_I		0x05500000

#define ARM_INST_LDRB_R		0x07d00000

#define ARM_INST_LDRH_I		0x01d000b0

#define ARM_INST_LDRD_I		0x014000d0

#define ARM_INST_LDRH_I		0x015000b0

#define ARM_INST_LDRH_R		0x019000b0

#define ARM_INST_LDR_I		0x05900000

#define ARM_INST_LDR_I		0x05100000

#define ARM_INST_LDR_R		0x07900000



#define ARM_INST_LDM		0x08900000
@@ -124,9 +127,10 @@ 
#define ARM_INST_SBC_R		0x00c00000

#define ARM_INST_SBCS_R		0x00d00000



#define ARM_INST_STR_I		0x05800000

#define ARM_INST_STRB_I		0x05c00000

#define ARM_INST_STRH_I		0x01c000b0

#define ARM_INST_STR_I		0x05000000

#define ARM_INST_STRB_I		0x05400000

#define ARM_INST_STRD_I		0x014000f0

#define ARM_INST_STRH_I		0x014000b0



#define ARM_INST_TST_R		0x01100000

#define ARM_INST_TST_I		0x03100000
@@ -183,17 +187,18 @@ 
#define ARM_EOR_R(rd, rn, rm)	_AL3_R(ARM_INST_EOR, rd, rn, rm)

#define ARM_EOR_I(rd, rn, imm)	_AL3_I(ARM_INST_EOR, rd, rn, imm)



#define ARM_LDR_I(rt, rn, off)	(ARM_INST_LDR_I | (rt) << 12 | (rn) << 16 \

				 | ((off) & 0xfff))

#define ARM_LDR_R(rt, rn, rm)	(ARM_INST_LDR_R | (rt) << 12 | (rn) << 16 \

#define ARM_LDR_R(rt, rn, rm)	(ARM_INST_LDR_R | ARM_INST_LDST__U \

				 | (rt) << 12 | (rn) << 16 \

				 | (rm))

#define ARM_LDRB_I(rt, rn, off)	(ARM_INST_LDRB_I | (rt) << 12 | (rn) << 16 \

				 | (off))

#define ARM_LDRB_R(rt, rn, rm)	(ARM_INST_LDRB_R | (rt) << 12 | (rn) << 16 \

#define ARM_LDR_R_SI(rt, rn, rm, type, imm) \

				(ARM_INST_LDR_R | ARM_INST_LDST__U \

				 | (rt) << 12 | (rn) << 16 \

				 | (imm) << 7 | (type) << 5 | (rm))

#define ARM_LDRB_R(rt, rn, rm)	(ARM_INST_LDRB_R | ARM_INST_LDST__U \

				 | (rt) << 12 | (rn) << 16 \

				 | (rm))

#define ARM_LDRH_I(rt, rn, off)	(ARM_INST_LDRH_I | (rt) << 12 | (rn) << 16 \

				 | (((off) & 0xf0) << 4) | ((off) & 0xf))

#define ARM_LDRH_R(rt, rn, rm)	(ARM_INST_LDRH_R | (rt) << 12 | (rn) << 16 \

#define ARM_LDRH_R(rt, rn, rm)	(ARM_INST_LDRH_R | ARM_INST_LDST__U \

				 | (rt) << 12 | (rn) << 16 \

				 | (rm))



#define ARM_LDM(rn, regs)	(ARM_INST_LDM | (rn) << 16 | (regs))
@@ -254,13 +259,6 @@ 
#define ARM_SUBS_I(rd, rn, imm)	_AL3_I(ARM_INST_SUBS, rd, rn, imm)

#define ARM_SBC_I(rd, rn, imm)	_AL3_I(ARM_INST_SBC, rd, rn, imm)



#define ARM_STR_I(rt, rn, off)	(ARM_INST_STR_I | (rt) << 12 | (rn) << 16 \

				 | ((off) & 0xfff))

#define ARM_STRH_I(rt, rn, off)	(ARM_INST_STRH_I | (rt) << 12 | (rn) << 16 \

				 | (((off) & 0xf0) << 4) | ((off) & 0xf))

#define ARM_STRB_I(rt, rn, off)	(ARM_INST_STRB_I | (rt) << 12 | (rn) << 16 \

				 | (((off) & 0xf0) << 4) | ((off) & 0xf))



#define ARM_TST_R(rn, rm)	_AL3_R(ARM_INST_TST, 0, rn, rm)

#define ARM_TST_I(rn, imm)	_AL3_I(ARM_INST_TST, 0, rn, imm)