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Commit 6fbab98e authored by Chetan C R's avatar Chetan C R
Browse files

ARM: dts: msm: Move cache, TLB dump tables to mem dump driver for SDM660 

Currently cpu cache and tlb dump tables are getting
allocated from cpuss dump driver. Unify all the dump
table allocations and move cpu cache dump table entries
to memory dump driver.
Currently cpu context and cpu scan dump entries are
getting added from watchdog driver. As part of
unification support for the mem-dump table entries, move
cpu context and scan dumps entries to mem-dump node for
sdm660 target.

Change-Id: I91eee70ae02b537ca5480fa4ec9baf1872621e86
parent b2afe8ce

qcom/sdm660.dtsi

+176 −140
Original line number Diff line number Diff line
@@ -63,16 +63,10 @@ 


			L1_I_0: l1-icache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x9040>;

			};



			L1_D_0: l1-dcache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x9040>;

			};



			L1_TLB_0: l1-tlb {

				qcom,dump-size = <0x2800>;

			};

		};
@@ -89,14 +83,9 @@ 
			next-level-cache = <&L2_0>;

			L1_I_1: l1-icache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x9040>;

			};

			L1_D_1: l1-dcache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x9040>;

			};

			L1_TLB_1: l1-tlb {

				qcom,dump-size = <0x2800>;

			};

		};
@@ -113,14 +102,9 @@ 
			#cooling-cells = <2>;

			L1_I_2: l1-icache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x9040>;

			};

			L1_D_2: l1-dcache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x9040>;

			};

			L1_TLB_2: l1-tlb {

				qcom,dump-size = <0x2800>;

			};

		};
@@ -137,14 +121,9 @@ 
			#cooling-cells = <2>;

			L1_I_3: l1-icache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x9040>;

			};

			L1_D_3: l1-dcache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x9040>;

			};

			L1_TLB_3: l1-tlb {

				qcom,dump-size = <0x2800>;

			};

		};
@@ -165,14 +144,9 @@ 
			};

			L1_I_100: l1-icache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x12000>;

			};

			L1_D_100: l1-dcache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x12000>;

			};

			L1_TLB_100: l1-tlb {

				qcom,dump-size = <0x4800>;

			};

		};
@@ -189,14 +163,9 @@ 
			next-level-cache = <&L2_1>;

			L1_I_101: l1-icache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x12000>;

			};

			L1_D_101: l1-dcache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x12000>;

			};

			L1_TLB_101: l1-tlb {

				qcom,dump-size = <0x4800>;

			};

		};
@@ -213,14 +182,9 @@ 
			next-level-cache = <&L2_1>;

			L1_I_102: l1-icache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x12000>;

			};

			L1_D_102: l1-dcache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x12000>;

			};

			L1_TLB_102: l1-tlb {

				qcom,dump-size = <0x4800>;

			};

		};
@@ -237,14 +201,9 @@ 
			next-level-cache = <&L2_1>;

			L1_I_103: l1-icache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x12000>;

			};

			L1_D_103: l1-dcache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x12000>;

			};

			L1_TLB_103: l1-tlb {

				qcom,dump-size = <0x4800>;

			};

		};
@@ -423,6 +382,14 @@ 
			reg = <0x0 0x94a00000 0x0 0x600000>;

		};



		dump_mem: mem_dump_region {

			compatible = "shared-dma-pool";

			alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;

			reusable;

			alignment = <0x0 0x400000>;

			size = <0x0 0x140000>;

		};



		venus_fw_mem: venus_fw_region {

			compatible = "shared-dma-pool";

			alloc-ranges = <0x0 0x80000000 0x0 0x20000000>;
@@ -572,102 +539,172 @@ 
		status = "ok";

	};



	cpuss_dump {

		compatible = "qcom,cpuss-dump";

		qcom,l1_i_cache0 {

			qcom,dump-node = <&L1_I_0>;

		mem_dump {

			compatible = "qcom,mem-dump";

			memory-region = <&dump_mem>;



			c_scandump {

				qcom,dump-size = <0x40000>;

				qcom,dump-id = <0xeb>;

			};



			c0_context {

				qcom,dump-size = <0x800>;

				qcom,dump-id = <0x0>;

			};



			c100_context {

				qcom,dump-size = <0x800>;

				qcom,dump-id = <0x1>;

			};



			c200_context {

				qcom,dump-size = <0x800>;

				qcom,dump-id = <0x2>;

			};



			c300_context {

				qcom,dump-size = <0x800>;

				qcom,dump-id = <0x3>;

			};



			c400_context {

				qcom,dump-size = <0x800>;

				qcom,dump-id = <0x4>;

			};



			c500_context {

				qcom,dump-size = <0x800>;

				qcom,dump-id = <0x5>;

			};



			c600_context {

				qcom,dump-size = <0x800>;

				qcom,dump-id = <0x6>;

			};



			c700_context {

				qcom,dump-size = <0x800>;

				qcom,dump-id = <0x7>;

			};



			l1_i_cache0 {

				qcom,dump-size = <0x9040>;

				qcom,dump-id = <0x60>;

			};

		qcom,l1_i_cache1 {

			qcom,dump-node = <&L1_I_1>;



			l1_i_cache1 {

				qcom,dump-size = <0x9040>;

				qcom,dump-id = <0x61>;

			};

		qcom,l1_i_cache2 {

			qcom,dump-node = <&L1_I_2>;



			l1_i_cache2 {

				qcom,dump-size = <0x9040>;

				qcom,dump-id = <0x62>;

			};

		qcom,l1_i_cache3 {

			qcom,dump-node = <&L1_I_3>;



			l1_i_cache3 {

				qcom,dump-size = <0x9040>;

				qcom,dump-id = <0x63>;

			};

		qcom,l1_i_cache100 {

			qcom,dump-node = <&L1_I_100>;



			l1_i_cache100 {

				qcom,dump-size = <0x12000>;

				qcom,dump-id = <0x64>;

			};

		qcom,l1_i_cache101 {

			qcom,dump-node = <&L1_I_101>;



			l1_i_cache101 {

				qcom,dump-size = <0x12000>;

				qcom,dump-id = <0x65>;

			};

		qcom,l1_i_cache102 {

			qcom,dump-node = <&L1_I_102>;



			l1_i_cache102 {

				qcom,dump-size = <0x12000>;

				qcom,dump-id = <0x66>;

			};

		qcom,l1_i_cache103 {

			qcom,dump-node = <&L1_I_103>;



			l1_i_cache103 {

				qcom,dump-size = <0x12000>;

				qcom,dump-id = <0x67>;

			};

		qcom,l1_d_cache0 {

			qcom,dump-node = <&L1_D_0>;



			l1_d_cache0 {

				qcom,dump-size = <0x9040>;

				qcom,dump-id = <0x80>;

			};

		qcom,l1_d_cache1 {

			qcom,dump-node = <&L1_D_1>;



			l1_d_cache1 {

				qcom,dump-size = <0x9040>;

				qcom,dump-id = <0x81>;

			};

		qcom,l1_d_cache2 {

			qcom,dump-node = <&L1_D_2>;



			l1_d_cache2 {

				qcom,dump-size = <0x9040>;

				qcom,dump-id = <0x82>;

			};

		qcom,l1_d_cache3 {

			qcom,dump-node = <&L1_D_3>;



			l1_d_cache3 {

				qcom,dump-size = <0x9040>;

				qcom,dump-id = <0x83>;

			};

		qcom,l1_d_cache100 {

			qcom,dump-node = <&L1_D_100>;



			l1_d_cache100 {

				qcom,dump-size = <0x12000>;

				qcom,dump-id = <0x84>;

			};

		qcom,l1_d_cache101 {

			qcom,dump-node = <&L1_D_101>;



			l1_d_cache101 {

				qcom,dump-size = <0x12000>;

				qcom,dump-id = <0x85>;

			};

		qcom,l1_d_cache102 {

			qcom,dump-node = <&L1_D_102>;



			l1_d_cache102 {

				qcom,dump-size = <0x12000>;

				qcom,dump-id = <0x86>;

			};

		qcom,l1_d_cache103 {

			qcom,dump-node = <&L1_D_103>;



			l1_d_cache103 {

				qcom,dump-size = <0x12000>;

				qcom,dump-id = <0x87>;

			};

		qcom,l1_tlb_dump0 {

			qcom,dump-node = <&L1_TLB_0>;



			l1_tlb_dump0 {

				qcom,dump-size = <0x2800>;

				qcom,dump-id = <0x20>;

			};

		qcom,l1_tlb_dump1 {

			qcom,dump-node = <&L1_TLB_1>;



			l1_tlb_dump1 {

				qcom,dump-size = <0x2800>;

				qcom,dump-id = <0x21>;

			};

		qcom,l1_tlb_dump2 {

			qcom,dump-node = <&L1_TLB_2>;



			l1_tlb_dump2 {

				qcom,dump-size = <0x2800>;

				qcom,dump-id = <0x22>;

			};

		qcom,l1_tlb_dump3 {

			qcom,dump-node = <&L1_TLB_3>;



			l1_tlb_dump3 {

				qcom,dump-size = <0x2800>;

				qcom,dump-id = <0x23>;

			};

		qcom,l1_tlb_dump100 {

			qcom,dump-node = <&L1_TLB_100>;



			l1_tlb_dump100 {

				qcom,dump-size = <0x4800>;

				qcom,dump-id = <0x24>;

			};

		qcom,l1_tlb_dump101 {

			qcom,dump-node = <&L1_TLB_101>;



			l1_tlb_dump101 {

				qcom,dump-size = <0x4800>;

				qcom,dump-id = <0x25>;

			};

		qcom,l1_tlb_dump102 {

			qcom,dump-node = <&L1_TLB_102>;



			l1_tlb_dump102 {

				qcom,dump-size = <0x4800>;

				qcom,dump-id = <0x26>;

			};

		qcom,l1_tlb_dump103 {

			qcom,dump-node = <&L1_TLB_103>;



			l1_tlb_dump103 {

				qcom,dump-size = <0x4800>;

				qcom,dump-id = <0x27>;

			};

	};
@@ -682,7 +719,6 @@ 
		qcom,pet-time = <10000>;

		qcom,ipi-ping;

		qcom,wakeup-enable;

		qcom,scandump-sizes = <0x40000>;

	};



	qcom,sps {