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Commit 6fa1c5f1 authored by Ville Syrjälä's avatar Ville Syrjälä
Browse files

drm/i915: Parametrize L3 error registers 



Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1446672017-24497-15-git-send-email-ville.syrjala@linux.intel.com


Reviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
parent 086f8e84

drivers/gpu/drm/i915/i915_gem.c

+3 −4
Original line number Diff line number Diff line
@@ -4574,7 +4574,6 @@ int i915_gem_l3_remap(struct drm_i915_gem_request *req, int slice) 
	struct intel_engine_cs *ring = req->ring;

	struct drm_device *dev = ring->dev;

	struct drm_i915_private *dev_priv = dev->dev_private;

	u32 reg_base = GEN7_L3LOG_BASE + (slice * 0x200);

	u32 *remap_info = dev_priv->l3_parity.remap_info[slice];

	int i, ret;
@@ -4590,10 +4589,10 @@ int i915_gem_l3_remap(struct drm_i915_gem_request *req, int slice) 
	 * here because no other code should access these registers other than

	 * at initialization time.

	 */

	for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) {

	for (i = 0; i < GEN7_L3LOG_SIZE / 4; i++) {

		intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));

		intel_ring_emit(ring, reg_base + i);

		intel_ring_emit(ring, remap_info[i/4]);

		intel_ring_emit(ring, GEN7_L3LOG(slice, i));

		intel_ring_emit(ring, remap_info[i]);

	}



	intel_ring_advance(ring);

drivers/gpu/drm/i915/i915_irq.c

+1 −1
Original line number Diff line number Diff line
@@ -1194,7 +1194,7 @@ static void ivybridge_parity_work(struct work_struct *work) 


		dev_priv->l3_parity.which_slice &= ~(1<<slice);



		reg = GEN7_L3CDERRST1 + (slice * 0x200);

		reg = GEN7_L3CDERRST1(slice);



		error_status = I915_READ(reg);

		row = GEN7_PARITY_ERROR_ROW(error_status);

drivers/gpu/drm/i915/i915_reg.h

+2 −4
Original line number Diff line number Diff line
@@ -6987,8 +6987,7 @@ enum skl_disp_power_wells { 
#define   GEN9_GAPS_TSV_CREDIT_DISABLE  (1<<7)



/* IVYBRIDGE DPF */

#define GEN7_L3CDERRST1			0xB008 /* L3CD Error Status 1 */

#define HSW_L3CDERRST11			0xB208 /* L3CD Error Status register 1 slice 1 */

#define GEN7_L3CDERRST1(slice)		(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */

#define   GEN7_L3CDERRST1_ROW_MASK	(0x7ff<<14)

#define   GEN7_PARITY_ERROR_VALID	(1<<13)

#define   GEN7_L3CDERRST1_BANK_MASK	(3<<11)
@@ -7001,8 +7000,7 @@ enum skl_disp_power_wells { 
		((reg & GEN7_L3CDERRST1_SUBBANK_MASK) >> 8)

#define   GEN7_L3CDERRST1_ENABLE	(1<<7)



#define GEN7_L3LOG_BASE			0xB070

#define HSW_L3LOG_BASE_SLICE1		0xB270

#define GEN7_L3LOG(slice, i)		(0xB070 + (slice) * 0x200 + (i) * 4)

#define GEN7_L3LOG_SIZE			0x80



#define GEN7_HALF_SLICE_CHICKEN1	0xe100 /* IVB GT1 + VLV */