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Commit 6f421e82 authored by Naveen Yadav's avatar Naveen Yadav
Browse files

ARM: dts: msm: Update various clock node and GDSC for Scuba 

Update the clock controller node and also update the GDSCs
for GCC and DISPCC.

Change-Id: Iee4ce3603d7f9e0c6413cacb8386da69aedc1a97
parent 8458de2c

qcom/scuba-gdsc.dtsi

+9 −9
Original line number Diff line number Diff line 
&soc {

	/* GDSCs in GCC */

	gcc_camss_top_gdsc: qcom,gdsc@1458004 {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		reg = <0x1458004 0x4>;

		regulator-name = "gcc_camss_top_gdsc";

		status = "disabled";

	};



	gcc_usb30_prim_gdsc: qcom,gdsc@141a004 {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		reg = <0x141a004 0x4>;

		regulator-name = "gcc_usb30_prim_gdsc";

		status = "disabled";

	};



	gcc_vcodec0_gdsc: qcom,gdsc@1458098 {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		reg = <0x1458098 0x4>;

		regulator-name = "gcc_vcodec0_gdsc";

		status = "disabled";

	};



	gcc_venus_gdsc: qcom,gdsc@145807c {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		reg = <0x145807c 0x4>;

		regulator-name = "gcc_venus_gdsc";

		status = "disabled";

	};



	hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc: qcom,gdsc@147d074 {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		reg = <0x147d074 0x4>;

		regulator-name = "hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc";

		qcom,no-status-check-on-disable;
@@ -38,7 +38,7 @@ 
	};



	hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc: qcom,gdsc@147d078 {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		reg = <0x147d078 0x4>;

		regulator-name = "hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc";

		qcom,no-status-check-on-disable;
@@ -47,7 +47,7 @@ 
	};



	hlos1_vote_turing_mmu_tbu1_gdsc: qcom,gdsc@147d060 {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		reg = <0x147d060 0x4>;

		regulator-name = "hlos1_vote_turing_mmu_tbu1_gdsc";

		qcom,no-status-check-on-disable;
@@ -56,7 +56,7 @@ 
	};



	hlos1_vote_turing_mmu_tbu0_gdsc: qcom,gdsc@147d07c {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		reg = <0x147d07c 0x4>;

		regulator-name = "hlos1_vote_turing_mmu_tbu0_gdsc";

		qcom,no-status-check-on-disable;
@@ -66,7 +66,7 @@ 


	/* GDSCs in DISPCC */

	mdss_core_gdsc: qcom,gdsc@5f03000 {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		reg = <0x5f03000 0x4>;

		regulator-name = "mdss_core_gdsc";

		proxy-supply = <&mdss_core_gdsc>;

qcom/scuba.dtsi

+12 −4
Original line number Diff line number Diff line
@@ -860,15 +860,23 @@ 
	};



	gcc: qcom,gcc@1400000 {

		compatible = "qcom,dummycc";

		clock-output-names = "gcc_clocks";

		compatible = "qcom,scuba-gcc", "syscon";

		reg = <0x1400000 0x1f0000>;

		reg-names = "cc_base";

		vdd_cx-supply = <&VDD_CX_LEVEL>;

		vdd_cx_ao-supply = <&VDD_CX_LEVEL_AO>;

		vdd_mx-supply = <&VDD_MX_LEVEL>;

		#clock-cells = <1>;

		#reset-cells = <1>;

	};



	dispcc: qcom,dispcc@5f00000 {

		compatible = "qcom,dummycc";

		clock-output-names = "dispcc_clocks";

		compatible = "qcom,scuba-dispcc", "syscon";

		reg = <0x5f00000 0x20000>;

		reg-names = "cc_base";

		clock-names = "cfg_ahb_clk";

		clocks = <&gcc GCC_DISP_AHB_CLK>;

		vdd_cx-supply = <&VDD_CX_LEVEL>;

		#clock-cells = <1>;

		#reset-cells = <1>;

	};