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Commit 6f329468 authored by David Daney's avatar David Daney Committed by Ralf Baechle
Browse files

MIPS: Give Octeon+ CPUs their own cputype. 



This allows us to treat them differently at runtime.

Signed-off-by: default avatarDavid Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/951/
Patchwork: http://patchwork.linux-mips.org/patch/987/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 6dd9344c

arch/mips/include/asm/cpu.h

+1 −1
Original line number Original line Diff line number Diff line
@@ -224,7 +224,7 @@ enum cpu_type_enum { 
	 * MIPS64 class processors

	 * MIPS64 class processors

	 */

	 */

	CPU_5KC, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2,

	CPU_5KC, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2,

	CPU_CAVIUM_OCTEON,

	CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS,





	CPU_LAST

	CPU_LAST

};

};

arch/mips/kernel/cpu-probe.c

+7 −2
Original line number Original line Diff line number Diff line
@@ -162,6 +162,7 @@ void __init check_wait(void) 
	case CPU_BCM6348:

	case CPU_BCM6348:

	case CPU_BCM6358:

	case CPU_BCM6358:

	case CPU_CAVIUM_OCTEON:

	case CPU_CAVIUM_OCTEON:

	case CPU_CAVIUM_OCTEON_PLUS:

		cpu_wait = r4k_wait;

		cpu_wait = r4k_wait;

		break;

		break;
@@ -911,12 +912,16 @@ static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu) 
	case PRID_IMP_CAVIUM_CN38XX:

	case PRID_IMP_CAVIUM_CN38XX:

	case PRID_IMP_CAVIUM_CN31XX:

	case PRID_IMP_CAVIUM_CN31XX:

	case PRID_IMP_CAVIUM_CN30XX:

	case PRID_IMP_CAVIUM_CN30XX:

		c->cputype = CPU_CAVIUM_OCTEON;

		__cpu_name[cpu] = "Cavium Octeon";

		goto platform;

	case PRID_IMP_CAVIUM_CN58XX:

	case PRID_IMP_CAVIUM_CN58XX:

	case PRID_IMP_CAVIUM_CN56XX:

	case PRID_IMP_CAVIUM_CN56XX:

	case PRID_IMP_CAVIUM_CN50XX:

	case PRID_IMP_CAVIUM_CN50XX:

	case PRID_IMP_CAVIUM_CN52XX:

	case PRID_IMP_CAVIUM_CN52XX:

		c->cputype = CPU_CAVIUM_OCTEON;

		c->cputype = CPU_CAVIUM_OCTEON_PLUS;

		__cpu_name[cpu] = "Cavium Octeon";

		__cpu_name[cpu] = "Cavium Octeon+";

platform:

		if (cpu == 0)

		if (cpu == 0)

			__elf_platform = "octeon";

			__elf_platform = "octeon";

		break;

		break;

arch/mips/mm/c-octeon.c

+4 −3
Original line number Original line Diff line number Diff line
@@ -183,6 +183,7 @@ static void __cpuinit probe_octeon(void) 




	switch (c->cputype) {

	switch (c->cputype) {

	case CPU_CAVIUM_OCTEON:

	case CPU_CAVIUM_OCTEON:

	case CPU_CAVIUM_OCTEON_PLUS:

		config1 = read_c0_config1();

		config1 = read_c0_config1();

		c->icache.linesz = 2 << ((config1 >> 19) & 7);

		c->icache.linesz = 2 << ((config1 >> 19) & 7);

		c->icache.sets = 64 << ((config1 >> 22) & 7);

		c->icache.sets = 64 << ((config1 >> 22) & 7);
@@ -192,10 +193,10 @@ static void __cpuinit probe_octeon(void) 
			c->icache.sets * c->icache.ways * c->icache.linesz;

			c->icache.sets * c->icache.ways * c->icache.linesz;

		c->icache.waybit = ffs(icache_size / c->icache.ways) - 1;

		c->icache.waybit = ffs(icache_size / c->icache.ways) - 1;

		c->dcache.linesz = 128;

		c->dcache.linesz = 128;

		if (OCTEON_IS_MODEL(OCTEON_CN3XXX))

		if (c->cputype == CPU_CAVIUM_OCTEON_PLUS)

			c->dcache.sets = 1; /* CN3XXX has one Dcache set */

		else

			c->dcache.sets = 2; /* CN5XXX has two Dcache sets */

			c->dcache.sets = 2; /* CN5XXX has two Dcache sets */

		else

			c->dcache.sets = 1; /* CN3XXX has one Dcache set */

		c->dcache.ways = 64;

		c->dcache.ways = 64;

		dcache_size =

		dcache_size =

			c->dcache.sets * c->dcache.ways * c->dcache.linesz;

			c->dcache.sets * c->dcache.ways * c->dcache.linesz;