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Commit 6f27ab3e authored by Elaine Zhang's avatar Elaine Zhang Committed by Heiko Stuebner
Browse files

soc: rockchip: support active_wakeup for rockchip power-domains 



Register gpd_dev_ops.active_wakeup function to support keep power
during suspend state. And add flag to each power domain to
decide whether keep power during suspend or not.

Signed-off-by: default avatarElaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
parent 29b4817d

drivers/soc/rockchip/pm_domains.c

+57 −43
Original line number Diff line number Diff line
@@ -27,6 +27,7 @@ struct rockchip_domain_info { 
	int req_mask;

	int idle_mask;

	int ack_mask;

	bool active_wakeup;

};



struct rockchip_pmu_info {
@@ -75,23 +76,24 @@ struct rockchip_pmu { 


#define to_rockchip_pd(gpd) container_of(gpd, struct rockchip_pm_domain, genpd)



#define DOMAIN(pwr, status, req, idle, ack)	\

#define DOMAIN(pwr, status, req, idle, ack, wakeup)	\

{						\

	.pwr_mask = (pwr >= 0) ? BIT(pwr) : 0,		\

	.status_mask = (status >= 0) ? BIT(status) : 0,	\

	.req_mask = (req >= 0) ? BIT(req) : 0,		\

	.idle_mask = (idle >= 0) ? BIT(idle) : 0,	\

	.ack_mask = (ack >= 0) ? BIT(ack) : 0,		\

	.active_wakeup = wakeup,			\

}



#define DOMAIN_RK3288(pwr, status, req)		\

	DOMAIN(pwr, status, req, req, (req) + 16)

#define DOMAIN_RK3288(pwr, status, req, wakeup)		\

	DOMAIN(pwr, status, req, req, (req) + 16, wakeup)



#define DOMAIN_RK3368(pwr, status, req)		\

	DOMAIN(pwr, status, req, (req) + 16, req)

#define DOMAIN_RK3368(pwr, status, req, wakeup)		\

	DOMAIN(pwr, status, req, (req) + 16, req, wakeup)



#define DOMAIN_RK3399(pwr, status, req)                \

	DOMAIN(pwr, status, req, req, req)

#define DOMAIN_RK3399(pwr, status, req, wakeup)		\

	DOMAIN(pwr, status, req, req, req, wakeup)



static bool rockchip_pmu_domain_is_idle(struct rockchip_pm_domain *pd)

{
@@ -295,6 +297,17 @@ static void rockchip_pd_detach_dev(struct generic_pm_domain *genpd, 
	pm_clk_destroy(dev);

}



static bool rockchip_active_wakeup(struct device *dev)

{

	struct generic_pm_domain *genpd;

	struct rockchip_pm_domain *pd;



	genpd = pd_to_genpd(dev->pm_domain);

	pd = container_of(genpd, struct rockchip_pm_domain, genpd);



	return pd->info->active_wakeup;

}



static int rockchip_pm_add_one_domain(struct rockchip_pmu *pmu,

				      struct device_node *node)

{
@@ -415,6 +428,7 @@ static int rockchip_pm_add_one_domain(struct rockchip_pmu *pmu, 
	pd->genpd.power_on = rockchip_pd_power_on;

	pd->genpd.attach_dev = rockchip_pd_attach_dev;

	pd->genpd.detach_dev = rockchip_pd_detach_dev;

	pd->genpd.dev_ops.active_wakeup = rockchip_active_wakeup;

	pd->genpd.flags = GENPD_FLAG_PM_CLK;

	pm_genpd_init(&pd->genpd, NULL, false);
@@ -623,48 +637,48 @@ static int rockchip_pm_domain_probe(struct platform_device *pdev) 
}



static const struct rockchip_domain_info rk3288_pm_domains[] = {

	[RK3288_PD_VIO]		= DOMAIN_RK3288(7, 7, 4),

	[RK3288_PD_HEVC]	= DOMAIN_RK3288(14, 10, 9),

	[RK3288_PD_VIDEO]	= DOMAIN_RK3288(8, 8, 3),

	[RK3288_PD_GPU]		= DOMAIN_RK3288(9, 9, 2),

	[RK3288_PD_VIO]		= DOMAIN_RK3288(7, 7, 4, false),

	[RK3288_PD_HEVC]	= DOMAIN_RK3288(14, 10, 9, false),

	[RK3288_PD_VIDEO]	= DOMAIN_RK3288(8, 8, 3, false),

	[RK3288_PD_GPU]		= DOMAIN_RK3288(9, 9, 2, false),

};



static const struct rockchip_domain_info rk3368_pm_domains[] = {

	[RK3368_PD_PERI]	= DOMAIN_RK3368(13, 12, 6),

	[RK3368_PD_VIO]		= DOMAIN_RK3368(15, 14, 8),

	[RK3368_PD_VIDEO]	= DOMAIN_RK3368(14, 13, 7),

	[RK3368_PD_GPU_0]	= DOMAIN_RK3368(16, 15, 2),

	[RK3368_PD_GPU_1]	= DOMAIN_RK3368(17, 16, 2),

	[RK3368_PD_PERI]	= DOMAIN_RK3368(13, 12, 6, true),

	[RK3368_PD_VIO]		= DOMAIN_RK3368(15, 14, 8, false),

	[RK3368_PD_VIDEO]	= DOMAIN_RK3368(14, 13, 7, false),

	[RK3368_PD_GPU_0]	= DOMAIN_RK3368(16, 15, 2, false),

	[RK3368_PD_GPU_1]	= DOMAIN_RK3368(17, 16, 2, false),

};



static const struct rockchip_domain_info rk3399_pm_domains[] = {

	[RK3399_PD_TCPD0]	= DOMAIN_RK3399(8, 8, -1),

	[RK3399_PD_TCPD1]	= DOMAIN_RK3399(9, 9, -1),

	[RK3399_PD_CCI]		= DOMAIN_RK3399(10, 10, -1),

	[RK3399_PD_CCI0]	= DOMAIN_RK3399(-1, -1, 15),

	[RK3399_PD_CCI1]	= DOMAIN_RK3399(-1, -1, 16),

	[RK3399_PD_PERILP]	= DOMAIN_RK3399(11, 11, 1),

	[RK3399_PD_PERIHP]	= DOMAIN_RK3399(12, 12, 2),

	[RK3399_PD_CENTER]	= DOMAIN_RK3399(13, 13, 14),

	[RK3399_PD_VIO]		= DOMAIN_RK3399(14, 14, 17),

	[RK3399_PD_GPU]		= DOMAIN_RK3399(15, 15, 0),

	[RK3399_PD_VCODEC]	= DOMAIN_RK3399(16, 16, 3),

	[RK3399_PD_VDU]		= DOMAIN_RK3399(17, 17, 4),

	[RK3399_PD_RGA]		= DOMAIN_RK3399(18, 18, 5),

	[RK3399_PD_IEP]		= DOMAIN_RK3399(19, 19, 6),

	[RK3399_PD_VO]		= DOMAIN_RK3399(20, 20, -1),

	[RK3399_PD_VOPB]	= DOMAIN_RK3399(-1, -1, 7),

	[RK3399_PD_VOPL]	= DOMAIN_RK3399(-1, -1, 8),

	[RK3399_PD_ISP0]	= DOMAIN_RK3399(22, 22, 9),

	[RK3399_PD_ISP1]	= DOMAIN_RK3399(23, 23, 10),

	[RK3399_PD_HDCP]	= DOMAIN_RK3399(24, 24, 11),

	[RK3399_PD_GMAC]	= DOMAIN_RK3399(25, 25, 23),

	[RK3399_PD_EMMC]	= DOMAIN_RK3399(26, 26, 24),

	[RK3399_PD_USB3]	= DOMAIN_RK3399(27, 27, 12),

	[RK3399_PD_EDP]		= DOMAIN_RK3399(28, 28, 22),

	[RK3399_PD_GIC]		= DOMAIN_RK3399(29, 29, 27),

	[RK3399_PD_SD]		= DOMAIN_RK3399(30, 30, 28),

	[RK3399_PD_SDIOAUDIO]	= DOMAIN_RK3399(31, 31, 29),

	[RK3399_PD_TCPD0]	= DOMAIN_RK3399(8, 8, -1, false),

	[RK3399_PD_TCPD1]	= DOMAIN_RK3399(9, 9, -1, false),

	[RK3399_PD_CCI]		= DOMAIN_RK3399(10, 10, -1, true),

	[RK3399_PD_CCI0]	= DOMAIN_RK3399(-1, -1, 15, true),

	[RK3399_PD_CCI1]	= DOMAIN_RK3399(-1, -1, 16, true),

	[RK3399_PD_PERILP]	= DOMAIN_RK3399(11, 11, 1, true),

	[RK3399_PD_PERIHP]	= DOMAIN_RK3399(12, 12, 2, true),

	[RK3399_PD_CENTER]	= DOMAIN_RK3399(13, 13, 14, true),

	[RK3399_PD_VIO]		= DOMAIN_RK3399(14, 14, 17, false),

	[RK3399_PD_GPU]		= DOMAIN_RK3399(15, 15, 0, false),

	[RK3399_PD_VCODEC]	= DOMAIN_RK3399(16, 16, 3, false),

	[RK3399_PD_VDU]		= DOMAIN_RK3399(17, 17, 4, false),

	[RK3399_PD_RGA]		= DOMAIN_RK3399(18, 18, 5, false),

	[RK3399_PD_IEP]		= DOMAIN_RK3399(19, 19, 6, false),

	[RK3399_PD_VO]		= DOMAIN_RK3399(20, 20, -1, false),

	[RK3399_PD_VOPB]	= DOMAIN_RK3399(-1, -1, 7, false),

	[RK3399_PD_VOPL]	= DOMAIN_RK3399(-1, -1, 8, false),

	[RK3399_PD_ISP0]	= DOMAIN_RK3399(22, 22, 9, false),

	[RK3399_PD_ISP1]	= DOMAIN_RK3399(23, 23, 10, false),

	[RK3399_PD_HDCP]	= DOMAIN_RK3399(24, 24, 11, false),

	[RK3399_PD_GMAC]	= DOMAIN_RK3399(25, 25, 23, true),

	[RK3399_PD_EMMC]	= DOMAIN_RK3399(26, 26, 24, true),

	[RK3399_PD_USB3]	= DOMAIN_RK3399(27, 27, 12, true),

	[RK3399_PD_EDP]		= DOMAIN_RK3399(28, 28, 22, false),

	[RK3399_PD_GIC]		= DOMAIN_RK3399(29, 29, 27, true),

	[RK3399_PD_SD]		= DOMAIN_RK3399(30, 30, 28, true),

	[RK3399_PD_SDIOAUDIO]	= DOMAIN_RK3399(31, 31, 29, true),

};



static const struct rockchip_pmu_info rk3288_pmu = {