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Commit 6e17b418 authored by Krzysztof Adamski's avatar Krzysztof Adamski Committed by Maxime Ripard
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clk: sunxi: Add apb0 gates for H3 



This patch adds support for APB0 in H3. It seems to be compatible with
earlier SOCs. apb0 gates controls R_ block peripherals (R_PIO, R_IR,
etc).

Since this gates behave just like any Allwinner clock gate, add a generic
compatible that can be reused if we don't have any clock to protect.

Signed-off-by: default avatarKrzysztof Adamski <k@japko.eu>
[Maxime: Removed the H3 compatible from the simple-gates driver, reworked
         the commit log a bit]
Signed-off-by: default avatarMaxime Ripard <maxime.ripard@free-electrons.com>
parent d331328d

Documentation/devicetree/bindings/clock/sunxi.txt

+2 −0
Original line number Diff line number Diff line
@@ -18,6 +18,7 @@ Required properties: 
	"allwinner,sun4i-a10-cpu-clk" - for the CPU multiplexer clock

	"allwinner,sun4i-a10-axi-clk" - for the AXI clock

	"allwinner,sun8i-a23-axi-clk" - for the AXI clock on A23

	"allwinner,sun4i-a10-gates-clk" - for generic gates on all compatible SoCs

	"allwinner,sun4i-a10-axi-gates-clk" - for the AXI gates

	"allwinner,sun4i-a10-ahb-clk" - for the AHB clock

	"allwinner,sun5i-a13-ahb-clk" - for the AHB clock on A13
@@ -46,6 +47,7 @@ Required properties: 
	"allwinner,sun6i-a31-apb0-gates-clk" - for the APB0 gates on A31

	"allwinner,sun7i-a20-apb0-gates-clk" - for the APB0 gates on A20

	"allwinner,sun8i-a23-apb0-gates-clk" - for the APB0 gates on A23

	"allwinner,sun8i-h3-apb0-gates-clk" - for the APB0 gates on H3

	"allwinner,sun9i-a80-apb0-gates-clk" - for the APB0 gates on A80

	"allwinner,sun4i-a10-apb1-clk" - for the APB1 clock

	"allwinner,sun9i-a80-apb1-clk" - for the APB1 bus clock on A80

drivers/clk/sunxi/clk-simple-gates.c

+2 −0
Original line number Diff line number Diff line
@@ -98,6 +98,8 @@ static void __init sunxi_simple_gates_init(struct device_node *node) 
	sunxi_simple_gates_setup(node, NULL, 0);

}



CLK_OF_DECLARE(sun4i_a10_gates, "allwinner,sun4i-a10-gates-clk",

	       sunxi_simple_gates_init);

CLK_OF_DECLARE(sun4i_a10_apb0, "allwinner,sun4i-a10-apb0-gates-clk",

	       sunxi_simple_gates_init);

CLK_OF_DECLARE(sun4i_a10_apb1, "allwinner,sun4i-a10-apb1-gates-clk",