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Commit 6da867e8 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: qcom: Enable LMH DCVSh and cpu isolate cooling devices for SCUBA"

parents f0aa3fa2 ab2188a5

qcom/scuba-thermal.dtsi

+60 −0
Original line number Diff line number Diff line 
#include <dt-bindings/thermal/thermal.h>

#include <dt-bindings/thermal/qmi_thermal.h>



&cpufreq_hw {

	#address-cells = <1>;

	#size-cells = <1>;

	lmh_dcvs0: qcom,limits-dcvs@f550800 {

		compatible = "qcom,msm-hw-limits";

		interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;

		qcom,affinity = <0>;

		reg = <0xf550800 0x1000>,

			<0xf521000 0x1000>;

		qcom,no-cooling-device-register;

	};



	qcom,cpu-isolation {

		compatible = "qcom,cpu-isolate";

		cpu0_isolate: cpu0-isolate {

			qcom,cpu = <&CPU0>;

			#cooling-cells = <2>;

		};



		cpu1_isolate: cpu1-isolate {

			qcom,cpu = <&CPU1>;

			#cooling-cells = <2>;

		};



		cpu2_isolate: cpu2-isolate {

			qcom,cpu = <&CPU2>;

			#cooling-cells = <2>;

		};



		cpu3_isolate: cpu3-isolate {

			qcom,cpu = <&CPU3>;

			#cooling-cells = <2>;

		};

	};

};



&soc {

	qmi-tmd-devices {

		compatible = "qcom,qmi-cooling-devices";
@@ -417,6 +453,18 @@ 
				type = "passive";

			};

		};



		cooling-maps {

			cpu0_cdev {

				trip = <&cpu0_2_config>;

				cooling-device = <&cpu0_isolate 1 1>;

			};



			cpu2_cdev {

				trip = <&cpu0_2_config>;

				cooling-device = <&cpu2_isolate 1 1>;

			};

		};

	};



	cpuss-1-step {
@@ -433,6 +481,18 @@ 
				type = "passive";

			};

		};



		cooling-maps {

			cpu1_cdev {

				trip = <&cpu1_3_config>;

				cooling-device = <&cpu1_isolate 1 1>;

			};



			cpu3_cdev {

				trip = <&cpu1_3_config>;

				cooling-device = <&cpu3_isolate 1 1>;

			};

		};

	};



	mdm-0-step {

qcom/scuba.dtsi

+5 −0
Original line number Diff line number Diff line
@@ -39,6 +39,8 @@ 
			i-cache-size = <0x8000>;

			next-level-cache = <&L2_0>;

			qcom,freq-domain = <&cpufreq_hw 0 4>;

			qcom,lmh-dcvs = <&lmh_dcvs0>;

			#cooling-cells = <2>;

			L2_0: l2-cache {

				compatible = "arm,arch-cache";

				cache-size = <0x80000>;
@@ -65,6 +67,7 @@ 
			i-cache-size = <0x8000>;

			next-level-cache = <&L2_0>;

			qcom,freq-domain = <&cpufreq_hw 0 4>;

			qcom,lmh-dcvs = <&lmh_dcvs0>;



			L1_I_1: l1-icache {

				compatible = "arm,arch-cache";
@@ -86,6 +89,7 @@ 
			i-cache-size = <0x8000>;

			next-level-cache = <&L2_0>;

			qcom,freq-domain = <&cpufreq_hw 0 4>;

			qcom,lmh-dcvs = <&lmh_dcvs0>;



			L1_I_2: l1-icache {

				compatible = "arm,arch-cache";
@@ -107,6 +111,7 @@ 
			i-cache-size = <0x8000>;

			next-level-cache = <&L2_0>;

			qcom,freq-domain = <&cpufreq_hw 0 4>;

			qcom,lmh-dcvs = <&lmh_dcvs0>;



			L1_I_3: l1-icache {

				compatible = "arm,arch-cache";