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Commit 6d16dac8 authored by Yong Zhao's avatar Yong Zhao Committed by Alex Deucher
Browse files

drm/amdgpu: Set the correct value for PDEs/PTEs of ATC memory on Raven 



Without the additional bits set in PDEs/PTEs, the ATC memory access
would have failed on Raven.

Signed-off-by: default avatarYong Zhao <yong.zhao@amd.com>
Acked-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Reviewed-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent bb7a9c8d

drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c

+6 −3
Original line number Diff line number Diff line
@@ -328,9 +328,10 @@ static int amdgpu_vm_alloc_levels(struct amdgpu_device *adev, 
				AMDGPU_GEM_CREATE_SHADOW);



	if (vm->pte_support_ats) {

		init_value = AMDGPU_PTE_SYSTEM;

		init_value = AMDGPU_PTE_DEFAULT_ATC;

		if (level != adev->vm_manager.num_level - 1)

			init_value |= AMDGPU_PDE_PTE;



	}



	/* walk over the address space and allocate the page tables */
@@ -2017,7 +2018,7 @@ int amdgpu_vm_clear_freed(struct amdgpu_device *adev, 
		list_del(&mapping->list);



		if (vm->pte_support_ats)

			init_pte_value = AMDGPU_PTE_SYSTEM;

			init_pte_value = AMDGPU_PTE_DEFAULT_ATC;



		r = amdgpu_vm_bo_update_mapping(adev, NULL, NULL, vm,

						mapping->start, mapping->last,
@@ -2629,7 +2630,9 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, 


		if (adev->asic_type == CHIP_RAVEN) {

			vm->pte_support_ats = true;

			init_pde_value = AMDGPU_PTE_SYSTEM | AMDGPU_PDE_PTE;

			init_pde_value = AMDGPU_PTE_DEFAULT_ATC

					| AMDGPU_PDE_PTE;



		}

	} else

		vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode &

drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h

+10 −0
Original line number Diff line number Diff line
@@ -73,6 +73,16 @@ struct amdgpu_bo_list_entry; 
#define AMDGPU_PTE_MTYPE(a)    ((uint64_t)a << 57)

#define AMDGPU_PTE_MTYPE_MASK	AMDGPU_PTE_MTYPE(3ULL)



/* For Raven */

#define AMDGPU_MTYPE_CC 2



#define AMDGPU_PTE_DEFAULT_ATC  (AMDGPU_PTE_SYSTEM      \

                                | AMDGPU_PTE_SNOOPED    \

                                | AMDGPU_PTE_EXECUTABLE \

                                | AMDGPU_PTE_READABLE   \

                                | AMDGPU_PTE_WRITEABLE  \

                                | AMDGPU_PTE_MTYPE(AMDGPU_MTYPE_CC))



/* How to programm VM fault handling */

#define AMDGPU_VM_FAULT_STOP_NEVER	0

#define AMDGPU_VM_FAULT_STOP_FIRST	1