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Commit 6d04ee9d authored by Dmytro Laktyushkin's avatar Dmytro Laktyushkin Committed by Alex Deucher
Browse files

drm/amd/display: Restructuring and cleaning up DML 



Signed-off-by: default avatarDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: default avatarTony Cheng <Tony.Cheng@amd.com>
Acked-by: default avatarHarry Wentland <Harry.Wentland@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 19b7fe4a

drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_math.c

+16 −0
Original line number Diff line number Diff line
@@ -27,20 +27,36 @@ 


float dcn_bw_mod(const float arg1, const float arg2)

{

	if (arg1 != arg1)

		return arg2;

	if (arg2 != arg2)

		return arg1;

	return arg1 - arg1 * ((int) (arg1 / arg2));

}



float dcn_bw_min2(const float arg1, const float arg2)

{

	if (arg1 != arg1)

		return arg2;

	if (arg2 != arg2)

		return arg1;

	return arg1 < arg2 ? arg1 : arg2;

}



unsigned int dcn_bw_max(const unsigned int arg1, const unsigned int arg2)

{

	if (arg1 != arg1)

		return arg2;

	if (arg2 != arg2)

		return arg1;

	return arg1 > arg2 ? arg1 : arg2;

}

float dcn_bw_max2(const float arg1, const float arg2)

{

	if (arg1 != arg1)

		return arg2;

	if (arg2 != arg2)

		return arg1;

	return arg1 > arg2 ? arg1 : arg2;

}

drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c

+3 −100
Original line number Diff line number Diff line
@@ -386,10 +386,6 @@ static void pipe_ctx_to_e2e_pipe_params ( 
			- pipe->stream->timing.v_addressable

			- pipe->stream->timing.v_border_bottom

			- pipe->stream->timing.v_border_top;



	input->dest.vsync_plus_back_porch = pipe->stream->timing.v_total

			- pipe->stream->timing.v_addressable

			- pipe->stream->timing.v_front_porch;

	input->dest.pixel_rate_mhz = pipe->stream->timing.pix_clk_khz/1000.0;

	input->dest.vstartup_start = pipe->pipe_dlg_param.vstartup_start;

	input->dest.vupdate_offset = pipe->pipe_dlg_param.vupdate_offset;
@@ -459,9 +455,9 @@ static void dcn_bw_calc_rq_dlg_ttu( 
	/*todo: soc->sr_enter_plus_exit_time??*/

	dlg_sys_param.t_srx_delay_us = dc->dcn_ip->dcfclk_cstate_latency / v->dcf_clk_deep_sleep;



	dml_rq_dlg_get_rq_params(dml, &rq_param, input.pipe.src);

	extract_rq_regs(dml, rq_regs, rq_param);

	dml_rq_dlg_get_dlg_params(

	dml1_rq_dlg_get_rq_params(dml, &rq_param, input.pipe.src);

	dml1_extract_rq_regs(dml, rq_regs, rq_param);

	dml1_rq_dlg_get_dlg_params(

			dml,

			dlg_regs,

			ttu_regs,
@@ -474,96 +470,6 @@ static void dcn_bw_calc_rq_dlg_ttu( 
			pipe->plane_state->flip_immediate);

}



static void dcn_dml_wm_override(

		const struct dcn_bw_internal_vars *v,

		struct display_mode_lib *dml,

		struct dc_state *context,

		const struct resource_pool *pool)

{

	int i, in_idx, active_count;



	struct _vcs_dpi_display_e2e_pipe_params_st *input = kzalloc(pool->pipe_count * sizeof(struct _vcs_dpi_display_e2e_pipe_params_st),

								    GFP_KERNEL);

	struct wm {

		double urgent;

		struct _vcs_dpi_cstate_pstate_watermarks_st cpstate;

		double pte_meta_urgent;

	} a;





	for (i = 0, in_idx = 0; i < pool->pipe_count; i++) {

		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];



		if (!pipe->stream || !pipe->plane_state)

			continue;



		input[in_idx].clks_cfg.dcfclk_mhz = v->dcfclk;

		input[in_idx].clks_cfg.dispclk_mhz = v->dispclk;

		input[in_idx].clks_cfg.dppclk_mhz = v->dppclk;

		input[in_idx].clks_cfg.refclk_mhz = pool->ref_clock_inKhz / 1000;

		input[in_idx].clks_cfg.socclk_mhz = v->socclk;

		input[in_idx].clks_cfg.voltage = v->voltage_level;

		input[in_idx].dout.output_format = (v->output_format[in_idx] == dcn_bw_420) ? dm_420 : dm_444;

		input[in_idx].dout.output_type  = (v->output[in_idx] == dcn_bw_hdmi) ? dm_hdmi : dm_dp;

		//input[in_idx].dout.output_standard;

		switch (v->output_deep_color[in_idx]) {

		case dcn_bw_encoder_12bpc:

			input[in_idx].dout.output_bpc = dm_out_12;

		break;

		case dcn_bw_encoder_10bpc:

			input[in_idx].dout.output_bpc = dm_out_10;

		break;

		case dcn_bw_encoder_8bpc:

		default:

			input[in_idx].dout.output_bpc = dm_out_8;

		break;

		}

		pipe_ctx_to_e2e_pipe_params(pipe, &input[in_idx].pipe);

		dml_rq_dlg_get_rq_reg(

			dml,

			&pipe->rq_regs,

			input[in_idx].pipe.src);

		in_idx++;

	}

	active_count = in_idx;



	a.urgent = dml_wm_urgent_e2e(dml, input, active_count);

	a.cpstate = dml_wm_cstate_pstate_e2e(dml, input, active_count);

	a.pte_meta_urgent = dml_wm_pte_meta_urgent(dml, a.urgent);



	context->bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns =

			a.cpstate.cstate_exit_us * 1000;

	context->bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns =

			a.cpstate.cstate_enter_plus_exit_us * 1000;

	context->bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns =

			a.cpstate.pstate_change_us * 1000;

	context->bw.dcn.watermarks.a.pte_meta_urgent_ns = a.pte_meta_urgent * 1000;

	context->bw.dcn.watermarks.a.urgent_ns = a.urgent * 1000;

	context->bw.dcn.watermarks.b = context->bw.dcn.watermarks.a;

	context->bw.dcn.watermarks.c = context->bw.dcn.watermarks.a;

	context->bw.dcn.watermarks.d = context->bw.dcn.watermarks.a;





	for (i = 0, in_idx = 0; i < pool->pipe_count; i++) {

		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];



		if (!pipe->stream || !pipe->plane_state)

			continue;



		dml_rq_dlg_get_dlg_reg(dml,

			&pipe->dlg_regs,

			&pipe->ttu_regs,

			input, active_count,

			in_idx,

			true,

			true,

			v->pte_enable == dcn_bw_yes,

			pipe->plane_state->flip_immediate);

		in_idx++;

	}

	kfree(input);

}



static void split_stream_across_pipes(

		struct resource_context *res_ctx,

		const struct resource_pool *pool,
@@ -1163,9 +1069,6 @@ bool dcn_validate_bandwidth( 


			input_idx++;

		}

		if (dc->debug.use_dml_wm)

			dcn_dml_wm_override(v, (struct display_mode_lib *)

					&dc->dml, context, pool);

	}



	if (v->voltage_level == 0) {

drivers/gpu/drm/amd/display/dc/dc.h

+0 −1
Original line number Diff line number Diff line
@@ -200,7 +200,6 @@ struct dc_debug { 
	bool disable_hubp_power_gate;

	bool disable_pplib_wm_range;

	enum wm_report_mode pplib_wm_report_mode;

	bool use_dml_wm;

	unsigned int min_disp_clk_khz;

	int sr_exit_time_dpm0_ns;

	int sr_enter_plus_exit_time_dpm0_ns;

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c

+1 −4
Original line number Diff line number Diff line
@@ -425,8 +425,6 @@ static const struct dc_debug debug_defaults_drv = { 
		.disable_pplib_clock_request = true,

		.disable_pplib_wm_range = false,

		.pplib_wm_report_mode = WM_REPORT_DEFAULT,

		.use_dml_wm = false,



		.pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP,

		.disable_dcc = DCC_ENABLE,

		.voltage_align_fclk = true,
@@ -439,8 +437,7 @@ static const struct dc_debug debug_defaults_diags = { 
		.clock_trace = true,

		.disable_stutter = true,

		.disable_pplib_clock_request = true,

		.disable_pplib_wm_range = true,

		.use_dml_wm = false,

		.disable_pplib_wm_range = true

};



static void dcn10_dpp_destroy(struct transform **xfm)

drivers/gpu/drm/amd/display/dc/dml/Makefile

+4 −4
Original line number Diff line number Diff line
@@ -3,19 +3,19 @@ 
# It provides the general basic services required by other DAL

# subcomponents.



CFLAGS_display_mode_vba.o := -mhard-float -msse -mpreferred-stack-boundary=4

CFLAGS_display_mode_lib.o := -mhard-float -msse -mpreferred-stack-boundary=4

CFLAGS_display_pipe_clocks.o := -mhard-float -msse -mpreferred-stack-boundary=4

CFLAGS_display_rq_dlg_calc.o := -mhard-float -msse -mpreferred-stack-boundary=4

CFLAGS_dml1_display_rq_dlg_calc.o := -mhard-float -msse -mpreferred-stack-boundary=4

CFLAGS_display_rq_dlg_helpers.o := -mhard-float -msse -mpreferred-stack-boundary=4

CFLAGS_display_watermark.o := -mhard-float -msse -mpreferred-stack-boundary=4

CFLAGS_soc_bounding_box.o := -mhard-float -msse -mpreferred-stack-boundary=4

CFLAGS_dml_common_defs.o := -mhard-float -msse -mpreferred-stack-boundary=4

CFLAGS_display_mode_support.o := -mhard-float -msse -mpreferred-stack-boundary=4





DML = display_mode_lib.o display_pipe_clocks.o display_rq_dlg_calc.o \

	  display_rq_dlg_helpers.o display_watermark.o \

	  soc_bounding_box.o dml_common_defs.o display_mode_support.o

	  display_rq_dlg_helpers.o dml1_display_rq_dlg_calc.o \

	  soc_bounding_box.o dml_common_defs.o display_mode_vba.o



AMD_DAL_DML = $(addprefix $(AMDDALPATH)/dc/dml/,$(DML))