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Commit 6cf75178 authored by Damien Lespiau's avatar Damien Lespiau Committed by Daniel Vetter
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drm/i915/skl: Make sure to break when not finding suitable PLL dividers



Right now, when finishing the cycle with odd dividers without finding a
suitable candidate, we end up in an infinite loop. Make sure to break in
that case.

Signed-off-by: default avatarDamien Lespiau <damien.lespiau@intel.com>
Reviewed-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent ea875496
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+4 −0
Original line number Diff line number Diff line
@@ -1184,6 +1184,10 @@ skl_ddi_calculate_wrpll(int clock /* in Hz */,
		}

		if (min_dco_index > 2 && dco_count == 2) {
                        /* oh well, we tried... */
                        if (retry_with_odd)
                                break;

			retry_with_odd = true;
			dco_count = 0;
		}