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Commit 6cd94d5e authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc 

Pull ARM SoC platform changes from Arnd Bergmann:
 "New and updated SoC support, notable changes include:

   - bcm:
        brcmstb SMP support
        initial iproc/cygnus support
   - exynos:
        Exynos4415 SoC support
        PMU and suspend support for Exynos5420
        PMU support for Exynos3250
        pm related maintenance
   - imx:
        new LS1021A SoC support
        vybrid 610 global timer support
   - integrator:
        convert to using multiplatform configuration
   - mediatek:
        earlyprintk support for mt8127/mt8135
   - meson:
        meson8 soc and l2 cache controller support
   - mvebu:
        Armada 38x CPU hotplug support
        drop support for prerelease Armada 375 Z1 stepping
        extended suspend support, now works on Armada 370/XP
   - omap:
        hwmod related maintenance
        prcm cleanup
   - pxa:
        initial pxa27x DT handling
   - rockchip:
        SMP support for rk3288
        add cpu frequency scaling support
   - shmobile:
        r8a7740 power domain support
        various small restart, timer, pci apmu changes
   - sunxi:
        Allwinner A80 (sun9i) earlyprintk support
   - ux500:
        power domain support

  Overall, a significant chunk of changes, coming mostly from the usual
  suspects: omap, shmobile, samsung and mvebu, all of which already
  contain a lot of platform specific code in arch/arm"

* tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (187 commits)
  ARM: mvebu: use the cpufreq-dt platform_data for independent clocks
  soc: integrator: Add terminating entry for integrator_cm_match
  ARM: mvebu: add SDRAM controller description for Armada XP
  ARM: mvebu: adjust mbus controller description on Armada 370/XP
  ARM: mvebu: add suspend/resume DT information for Armada XP GP
  ARM: mvebu: synchronize secondary CPU clocks on resume
  ARM: mvebu: make sure MMU is disabled in armada_370_xp_cpu_resume
  ARM: mvebu: Armada XP GP specific suspend/resume code
  ARM: mvebu: reserve the first 10 KB of each memory bank for suspend/resume
  ARM: mvebu: implement suspend/resume support for Armada XP
  clk: mvebu: add suspend/resume for gatable clocks
  bus: mvebu-mbus: provide a mechanism to save SDRAM window configuration
  bus: mvebu-mbus: suspend/resume support
  clocksource: time-armada-370-xp: add suspend/resume support
  irqchip: armada-370-xp: Add suspend/resume support
  ARM: add lolevel debug support for asm9260
  ARM: add mach-asm9260
  ARM: EXYNOS: use u8 for val[] in struct exynos_pmu_conf
  power: reset: imx-snvs-poweroff: add power off driver for i.mx6
  ARM: imx: temporarily remove CONFIG_SOC_FSL from LS1021A
  ...
parents 6c9e9247 842f7d2c

Documentation/arm/firmware.txt

+5 −23
Original line number Diff line number Diff line
@@ -7,32 +7,14 @@ world, which changes the way some things have to be initialized. This makes 
a need to provide an interface for such platforms to specify available firmware

operations and call them when needed.



Firmware operations can be specified using struct firmware_ops



	struct firmware_ops {

		/*

		* Enters CPU idle mode

		*/

		int (*do_idle)(void);

		/*

		* Sets boot address of specified physical CPU

		*/

		int (*set_cpu_boot_addr)(int cpu, unsigned long boot_addr);

		/*

		* Boots specified physical CPU

		*/

		int (*cpu_boot)(int cpu);

		/*

		* Initializes L2 cache

		*/

		int (*l2x0_init)(void);

	};



and then registered with register_firmware_ops function

Firmware operations can be specified by filling in a struct firmware_ops

with appropriate callbacks and then registering it with register_firmware_ops()

function.



	void register_firmware_ops(const struct firmware_ops *ops)



the ops pointer must be non-NULL.

The ops pointer must be non-NULL. More information about struct firmware_ops

and its members can be found in arch/arm/include/asm/firmware.h header.



There is a default, empty set of operations provided, so there is no need to

set anything if platform does not require firmware operations.

Documentation/arm/sunxi/README

+13 −3
Original line number Diff line number Diff line
@@ -37,16 +37,26 @@ SunXi family 
          http://dl.linux-sunxi.org/A20/A20%20User%20Manual%202013-03-22.pdf



      - Allwinner A23

        + Not Supported

        + Datasheet

          http://dl.linux-sunxi.org/A23/A23%20Datasheet%20V1.0%2020130830.pdf

        + User Manual

          http://dl.linux-sunxi.org/A23/A23%20User%20Manual%20V1.0%2020130830.pdf



    * Quad ARM Cortex-A7 based SoCs

      - Allwinner A31 (sun6i)

        + Datasheet

          http://dl.linux-sunxi.org/A31/A31%20Datasheet%20-%20v1.00%20(2012-12-24).pdf

          http://dl.linux-sunxi.org/A31/A3x_release_document/A31/IC/A31%20datasheet%20V1.3%2020131106.pdf

        + User Manual

          http://dl.linux-sunxi.org/A31/A3x_release_document/A31/IC/A31%20user%20manual%20V1.1%2020130630.pdf



      - Allwinner A31s (sun6i)

        + Not Supported

        + Datasheet

          http://dl.linux-sunxi.org/A31/A3x_release_document/A31s/IC/A31s%20datasheet%20V1.3%2020131106.pdf

        + User Manual

          http://dl.linux-sunxi.org/A31/A3x_release_document/A31s/IC/A31s%20User%20Manual%20%20V1.0%2020130322.pdf



    * Quad ARM Cortex-A15, Quad ARM Cortex-A7 based SoCs

      - Allwinner A80

        + Not Supported
 
 No newline at end of file
 
        + Datasheet

	  http://dl.linux-sunxi.org/A80/A80_Datasheet_Revision_1.0_0404.pdf

Documentation/devicetree/bindings/arm/amlogic.txt

+5 −3
Original line number Diff line number Diff line
@@ -2,7 +2,9 @@ Amlogic MesonX device tree bindings 
-------------------------------------------



Boards with the Amlogic Meson6 SoC shall have the following properties:



  Required root node property:

    compatible: "amlogic,meson6"



compatible = "amlogic,meson6";
 
Boards with the Amlogic Meson8 SoC shall have the following properties:

  Required root node property:

    compatible: "amlogic,meson8";

Documentation/devicetree/bindings/arm/cpus.txt

+9 −0
Original line number Diff line number Diff line
@@ -227,6 +227,15 @@ nodes to be present and contain the properties described below. 
			# List of phandles to idle state nodes supported

			  by this cpu [3].



	- rockchip,pmu

		Usage: optional for systems that have an "enable-method"

		       property value of "rockchip,rk3066-smp"

		       While optional, it is the preferred way to get access to

		       the cpu-core power-domains.

		Value type: <phandle>

		Definition: Specifies the syscon node controlling the cpu core

			    power domains.



Example 1 (dual-cluster big.LITTLE system 32-bit):



	cpus {

Documentation/devicetree/bindings/arm/sunxi.txt

0 → 100644
+12 −0
Original line number Diff line number Diff line 
Allwinner sunXi Platforms Device Tree Bindings



Each device tree must specify which Allwinner SoC it uses,

using one of the following compatible strings:



  allwinner,sun4i-a10

  allwinner,sun5i-a10s

  allwinner,sun5i-a13

  allwinner,sun6i-a31

  allwinner,sun7i-a20

  allwinner,sun8i-a23

  allwinner,sun9i-a80