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Commit 6c70faf1 authored by Sean Paul's avatar Sean Paul Committed by Thierry Reding
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drm: Fix warning when building docs for scdc_helper



Fixes:
../drivers/gpu/drm/drm_scdc_helper.c:203: ERROR: Unexpected indentation.
../drivers/gpu/drm/drm_scdc_helper.c:204: WARNING: Block quote ends without a blank line; unexpected unindent.

Changes in v2:
 - Property blockquote TMDS calculations so they look pretty (Daniel)
 - Remove duplicate documentation from the header file

Signed-off-by: default avatarSean Paul <seanpaul@chromium.org>
Reviewed-by: default avatarShashank Sharma <shashank.sharma@intel.com>
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170720200921.36897-1-seanpaul@chromium.org
parent 8d0873a2
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+20 −13
Original line number Diff line number Diff line
@@ -194,18 +194,25 @@ EXPORT_SYMBOL(drm_scdc_set_scrambling);
 * @adapter: I2C adapter for DDC channel
 * @set: ret or reset the high clock ratio
 *
 *
 *	TMDS clock ratio calculations go like this:
 *		TMDS character = 10 bit TMDS encoded value
 * TMDS character rate = The rate at which TMDS characters are transmitted(Mcsc)
 *
 *		TMDS character rate = The rate at which TMDS characters are
 *		transmitted (Mcsc)
 *
 *		TMDS bit rate = 10x TMDS character rate
 *
 *	As per the spec:
 * TMDS clock rate for pixel clock < 340 MHz = 1x the character rate
 *	= 1/10 pixel clock rate
 * TMDS clock rate for pixel clock > 340 MHz = 0.25x the character rate
 *	= 1/40 pixel clock rate
 *		TMDS clock rate for pixel clock < 340 MHz = 1x the character
 *		rate = 1/10 pixel clock rate
 *
 *		TMDS clock rate for pixel clock > 340 MHz = 0.25x the character
 *		rate = 1/40 pixel clock rate
 *
 *	Writes to the TMDS config register over SCDC channel, and:
 *		sets TMDS clock ratio to 1/40 when set = 1
 *
 *		sets TMDS clock ratio to 1/10 when set = 0
 *
 * Returns:
+0 −25
Original line number Diff line number Diff line
@@ -131,31 +131,6 @@ static inline int drm_scdc_writeb(struct i2c_adapter *adapter, u8 offset,

bool drm_scdc_get_scrambling_status(struct i2c_adapter *adapter);

/**
 * drm_scdc_set_scrambling - enable scrambling
 * @adapter: I2C adapter for DDC channel
 * @enable: bool to indicate if scrambling is to be enabled/disabled
 *
 * Writes the TMDS config register over SCDC channel, and:
 * enables scrambling when enable = 1
 * disables scrambling when enable = 0
 *
 * Returns:
 * True if scrambling is set/reset successfully, false otherwise.
 */
bool drm_scdc_set_scrambling(struct i2c_adapter *adapter, bool enable);

/**
 * drm_scdc_set_high_tmds_clock_ratio - set TMDS clock ratio
 * @adapter: I2C adapter for DDC channel
 * @set: ret or reset the high clock ratio
 *
 * Writes to the TMDS config register over SCDC channel, and:
 * sets TMDS clock ratio to 1/40 when set = 1
 * sets TMDS clock ratio to 1/10 when set = 0
 *
 * Returns:
 * True if write is successful, false otherwise.
 */
bool drm_scdc_set_high_tmds_clock_ratio(struct i2c_adapter *adapter, bool set);
#endif