Merge "msm: kgsl: Add RSC and PDC sequence changes for a650" (6bcc992e) · Commits · e / devices / android_kernel_oneplus_sm7250

drivers/gpu/msm/adreno-gpulist.h

+11 −1

Original line number	Original line	Diff line number	Diff line
	/* SPDX-License-Identifier: GPL-2.0 */		/* SPDX-License-Identifier: GPL-2.0 */
	/*		/*
	* Copyright (c) 2002,2007-2018, The Linux Foundation. All rights reserved.		* Copyright (c) 2002,2007-2019, The Linux Foundation. All rights reserved.
	*/		*/

	#define ANY_ID (~0)		#define ANY_ID (~0)
	@@ -332,6 +332,7 @@ static const struct adreno_gpu_core adreno_gpulist[] = {
	.gpmu_tsens = 0x000C000D,		.gpmu_tsens = 0x000C000D,
	.max_power = 5448,		.max_power = 5448,
	.prim_fifo_threshold = 0x0018000,		.prim_fifo_threshold = 0x0018000,
			.pdc_address_offset = 0x00030080,
	},		},
	{		{
	.gpurev = ADRENO_REV_A630,		.gpurev = ADRENO_REV_A630,
	@@ -354,6 +355,7 @@ static const struct adreno_gpu_core adreno_gpulist[] = {
	.gpmu_tsens = 0x000C000D,		.gpmu_tsens = 0x000C000D,
	.max_power = 5448,		.max_power = 5448,
	.prim_fifo_threshold = 0x0018000,		.prim_fifo_threshold = 0x0018000,
			.pdc_address_offset = 0x00030080,
	},		},
	{		{
	.gpurev = ADRENO_REV_A615,		.gpurev = ADRENO_REV_A615,
	@@ -374,6 +376,7 @@ static const struct adreno_gpu_core adreno_gpulist[] = {
	.gpmu_major = 0x1,		.gpmu_major = 0x1,
	.gpmu_minor = 0x003,		.gpmu_minor = 0x003,
	.prim_fifo_threshold = 0x0018000,		.prim_fifo_threshold = 0x0018000,
			.pdc_address_offset = 0x00030080,
	},		},
	{		{
	.gpurev = ADRENO_REV_A618,		.gpurev = ADRENO_REV_A618,
	@@ -394,6 +397,7 @@ static const struct adreno_gpu_core adreno_gpulist[] = {
	.gpmu_major = 0x1,		.gpmu_major = 0x1,
	.gpmu_minor = 0x007,		.gpmu_minor = 0x007,
	.prim_fifo_threshold = 0x0018000,		.prim_fifo_threshold = 0x0018000,
			.pdc_address_offset = 0x00030090,
	},		},
	{		{
	.gpurev = ADRENO_REV_A640,		.gpurev = ADRENO_REV_A640,
	@@ -417,6 +421,7 @@ static const struct adreno_gpu_core adreno_gpulist[] = {
	.max_power = 5448,		.max_power = 5448,
	.va_padding = SZ_64K,		.va_padding = SZ_64K,
	.prim_fifo_threshold = 0x00200000,		.prim_fifo_threshold = 0x00200000,
			.pdc_address_offset = 0x00030090,
	},		},
	{		{
	.gpurev = ADRENO_REV_A640,		.gpurev = ADRENO_REV_A640,
	@@ -439,6 +444,7 @@ static const struct adreno_gpu_core adreno_gpulist[] = {
	.gpmu_tsens = 0x000C000D,		.gpmu_tsens = 0x000C000D,
	.max_power = 5448,		.max_power = 5448,
	.prim_fifo_threshold = 0x00200000,		.prim_fifo_threshold = 0x00200000,
			.pdc_address_offset = 0x00030090,
	},		},
	{		{
	.gpurev = ADRENO_REV_A650,		.gpurev = ADRENO_REV_A650,
	@@ -459,6 +465,7 @@ static const struct adreno_gpu_core adreno_gpulist[] = {
	.gpmu_tsens = 0x000C000D,		.gpmu_tsens = 0x000C000D,
	.max_power = 5448,		.max_power = 5448,
	.prim_fifo_threshold = 0x00300000,		.prim_fifo_threshold = 0x00300000,
			.pdc_address_offset = 0x000300A0,
	},		},
	{		{
	.gpurev = ADRENO_REV_A680,		.gpurev = ADRENO_REV_A680,
	@@ -479,6 +486,7 @@ static const struct adreno_gpu_core adreno_gpulist[] = {
	.gpmu_tsens = 0x000C000D,		.gpmu_tsens = 0x000C000D,
	.max_power = 5448,		.max_power = 5448,
	.prim_fifo_threshold = 0x00400000,		.prim_fifo_threshold = 0x00400000,
			.pdc_address_offset = 0x00030090,
	},		},
	{		{
	.gpurev = ADRENO_REV_A612,		.gpurev = ADRENO_REV_A612,
	@@ -497,6 +505,7 @@ static const struct adreno_gpu_core adreno_gpulist[] = {
	.busy_mask = 0xFFFFFFFE,		.busy_mask = 0xFFFFFFFE,
	.gpmufw_name = "a612_rgmu.bin",		.gpmufw_name = "a612_rgmu.bin",
	.prim_fifo_threshold = 0x00080000,		.prim_fifo_threshold = 0x00080000,
			.pdc_address_offset = 0x00030080,
	},		},
	{		{
	.gpurev = ADRENO_REV_A616,		.gpurev = ADRENO_REV_A616,
	@@ -517,5 +526,6 @@ static const struct adreno_gpu_core adreno_gpulist[] = {
	.gpmu_major = 0x1,		.gpmu_major = 0x1,
	.gpmu_minor = 0x003,		.gpmu_minor = 0x003,
	.prim_fifo_threshold = 0x0018000,		.prim_fifo_threshold = 0x0018000,
			.pdc_address_offset = 0x00030080,
	},		},
	};		};

drivers/gpu/msm/adreno.h

+1 −0

Original line number	Original line	Diff line number	Diff line
	@@ -423,6 +423,7 @@ struct adreno_gpu_core {
	unsigned int max_power;		unsigned int max_power;
	uint64_t va_padding;		uint64_t va_padding;
	unsigned int prim_fifo_threshold;		unsigned int prim_fifo_threshold;
			unsigned int pdc_address_offset;
	};		};

drivers/gpu/msm/adreno_a6xx_gmu.c

+19 −18

Original line number	Original line	Diff line number	Diff line
	@@ -82,7 +82,7 @@ static int _load_gmu_rpmh_ucode(struct kgsl_device *device)
	struct adreno_device *adreno_dev = ADRENO_DEVICE(device);		struct adreno_device *adreno_dev = ADRENO_DEVICE(device);
	struct resource res_pdc, res_cfg, *res_seq;		struct resource res_pdc, res_cfg, *res_seq;
	void __iomem cfg = NULL, seq = NULL, *rscc;		void __iomem cfg = NULL, seq = NULL, *rscc;
	unsigned int cfg_offset, seq_offset, rscc_offset;		unsigned int cfg_offset, seq_offset;

	/* Offsets from the base PDC (if no PDC subsections in the DTSI) */		/* Offsets from the base PDC (if no PDC subsections in the DTSI) */
	if (adreno_is_a640v2(adreno_dev)) {		if (adreno_is_a640v2(adreno_dev)) {
	@@ -167,11 +167,19 @@ static int _load_gmu_rpmh_ucode(struct kgsl_device *device)
	_regwrite(rscc, A6XX_RSCC_TIMESTAMP_UNIT1_EN_DRV0, 1);		_regwrite(rscc, A6XX_RSCC_TIMESTAMP_UNIT1_EN_DRV0, 1);

	/* Load RSC sequencer uCode for sleep and wakeup */		/* Load RSC sequencer uCode for sleep and wakeup */
			if (adreno_is_a650(adreno_dev)) {
			_regwrite(rscc, A6XX_RSCC_SEQ_MEM_0_DRV0, 0xEAAAE5A0);
			_regwrite(rscc, A6XX_RSCC_SEQ_MEM_0_DRV0 + 1, 0xE1A1EBAB);
			_regwrite(rscc, A6XX_RSCC_SEQ_MEM_0_DRV0 + 2, 0xA2E0A581);
			_regwrite(rscc, A6XX_RSCC_SEQ_MEM_0_DRV0 + 3, 0xECAC82E2);
			_regwrite(rscc, A6XX_RSCC_SEQ_MEM_0_DRV0 + 4, 0x0020EDAD);
			} else {
	_regwrite(rscc, A6XX_RSCC_SEQ_MEM_0_DRV0, 0xA7A506A0);		_regwrite(rscc, A6XX_RSCC_SEQ_MEM_0_DRV0, 0xA7A506A0);
	_regwrite(rscc, A6XX_RSCC_SEQ_MEM_0_DRV0 + 1, 0xA1E6A6E7);		_regwrite(rscc, A6XX_RSCC_SEQ_MEM_0_DRV0 + 1, 0xA1E6A6E7);
	_regwrite(rscc, A6XX_RSCC_SEQ_MEM_0_DRV0 + 2, 0xA2E081E1);		_regwrite(rscc, A6XX_RSCC_SEQ_MEM_0_DRV0 + 2, 0xA2E081E1);
	_regwrite(rscc, A6XX_RSCC_SEQ_MEM_0_DRV0 + 3, 0xE9A982E2);		_regwrite(rscc, A6XX_RSCC_SEQ_MEM_0_DRV0 + 3, 0xE9A982E2);
	_regwrite(rscc, A6XX_RSCC_SEQ_MEM_0_DRV0 + 4, 0x0020E8A8);		_regwrite(rscc, A6XX_RSCC_SEQ_MEM_0_DRV0 + 4, 0x0020E8A8);
			}

	/* Load PDC sequencer uCode for power up and power down sequence */		/* Load PDC sequencer uCode for power up and power down sequence */
	_regwrite(seq, PDC_GPU_SEQ_MEM_0, 0xFEBEA1E1);		_regwrite(seq, PDC_GPU_SEQ_MEM_0, 0xFEBEA1E1);
	@@ -192,12 +200,8 @@ static int _load_gmu_rpmh_ucode(struct kgsl_device *device)
	_regwrite(cfg, PDC_GPU_TCS1_CMD0_DATA + PDC_CMD_OFFSET, 0x0);		_regwrite(cfg, PDC_GPU_TCS1_CMD0_DATA + PDC_CMD_OFFSET, 0x0);
	_regwrite(cfg, PDC_GPU_TCS1_CMD0_MSGID + PDC_CMD_OFFSET * 2, 0x10108);		_regwrite(cfg, PDC_GPU_TCS1_CMD0_MSGID + PDC_CMD_OFFSET * 2, 0x10108);

	if ((ADRENO_GPUREV(adreno_dev) >= 640) \|\| adreno_is_a618(adreno_dev))
	_regwrite(cfg, PDC_GPU_TCS1_CMD0_ADDR + PDC_CMD_OFFSET * 2,
	0x30090);
	else
	_regwrite(cfg, PDC_GPU_TCS1_CMD0_ADDR + PDC_CMD_OFFSET * 2,		_regwrite(cfg, PDC_GPU_TCS1_CMD0_ADDR + PDC_CMD_OFFSET * 2,
	0x30080);		adreno_dev->gpucore->pdc_address_offset);

	_regwrite(cfg, PDC_GPU_TCS1_CMD0_DATA + PDC_CMD_OFFSET * 2, 0x0);		_regwrite(cfg, PDC_GPU_TCS1_CMD0_DATA + PDC_CMD_OFFSET * 2, 0x0);
	_regwrite(cfg, PDC_GPU_TCS3_CMD_ENABLE_BANK, 7);		_regwrite(cfg, PDC_GPU_TCS3_CMD_ENABLE_BANK, 7);
	@@ -216,12 +220,9 @@ static int _load_gmu_rpmh_ucode(struct kgsl_device *device)

	_regwrite(cfg, PDC_GPU_TCS3_CMD0_MSGID + PDC_CMD_OFFSET * 2, 0x10108);		_regwrite(cfg, PDC_GPU_TCS3_CMD0_MSGID + PDC_CMD_OFFSET * 2, 0x10108);

	if ((ADRENO_GPUREV(adreno_dev) >= 640) \|\| adreno_is_a618(adreno_dev))
	_regwrite(cfg, PDC_GPU_TCS3_CMD0_ADDR + PDC_CMD_OFFSET * 2,		_regwrite(cfg, PDC_GPU_TCS3_CMD0_ADDR + PDC_CMD_OFFSET * 2,
	0x30090);		adreno_dev->gpucore->pdc_address_offset);
	else
	_regwrite(cfg, PDC_GPU_TCS3_CMD0_ADDR + PDC_CMD_OFFSET * 2,
	0x30080);
	_regwrite(cfg, PDC_GPU_TCS3_CMD0_DATA + PDC_CMD_OFFSET * 2, 0x3);		_regwrite(cfg, PDC_GPU_TCS3_CMD0_DATA + PDC_CMD_OFFSET * 2, 0x3);

	/* Setup GPU PDC */		/* Setup GPU PDC */