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Commit 6bc474de authored by Liviu Dudau's avatar Liviu Dudau Committed by Arnd Bergmann
Browse files

arm64: ARM: Fix the Generic Timers interrupt active level description



The Cortex-A5x TRM states in paragraph "9.2 Generic Timer functional
description" that generic timers provide an active-LOW interrupt
output. Fix the device trees to correctly describe this.

While doing this update the CPU mask to match the number of described
CPUs as well.

Signed-off-by: default avatarLiviu Dudau <Liviu.Dudau@arm.com>
Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parent 41904360
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+4 −4
Original line number Diff line number Diff line
@@ -78,10 +78,10 @@

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <1 13 0xff01>,
			     <1 14 0xff01>,
			     <1 11 0xff01>,
			     <1 10 0xff01>;
		interrupts = <1 13 0xf08>,
			     <1 14 0xf08>,
			     <1 11 0xf08>,
			     <1 10 0xf08>;
		clock-frequency = <100000000>;
	};

+4 −4
Original line number Diff line number Diff line
@@ -98,10 +98,10 @@

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_EDGE_RISING)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_EDGE_RISING)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_EDGE_RISING)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_EDGE_RISING)>;
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
	};

	pmu {
+4 −4
Original line number Diff line number Diff line
@@ -81,10 +81,10 @@

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <1 13 0xff01>,
			     <1 14 0xff01>,
			     <1 11 0xff01>,
			     <1 10 0xff01>;
		interrupts = <1 13 0xf08>,
			     <1 14 0xf08>,
			     <1 11 0xf08>,
			     <1 10 0xf08>;
		clock-frequency = <100000000>;
	};