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Commit 6b42e8d0 authored by Felix Fietkau's avatar Felix Fietkau Committed by John W. Linville
Browse files

ath9k_hw: fix fast clock handling for 5GHz channels 



Combine multiple checks that were supposed to check for the same
conditions, but didn't. Always enable fast PLL clock on AR9280 2.0

Signed-off-by: default avatarFelix Fietkau <nbd@openwrt.org>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent 5b75d0fc

drivers/net/wireless/ath/ath9k/ar5008_phy.c

+2 −3
Original line number Diff line number Diff line
@@ -850,7 +850,7 @@ static int ar5008_hw_process_ini(struct ath_hw *ah, 


	REG_WRITE_ARRAY(&ah->iniBB_RfGain, freqIndex, regWrites);



	if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {

	if (IS_CHAN_A_FAST_CLOCK(ah, chan)) {

		REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex,

				regWrites);

	}
@@ -892,8 +892,7 @@ static void ar5008_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan) 
		rfMode |= (IS_CHAN_5GHZ(chan)) ?

			AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;



	if ((AR_SREV_9280_20(ah) || AR_SREV_9300_20_OR_LATER(ah))

	    && IS_CHAN_A_5MHZ_SPACED(chan))

	if (IS_CHAN_A_FAST_CLOCK(ah, chan))

		rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);



	REG_WRITE(ah, AR_PHY_MODE, rfMode);

drivers/net/wireless/ath/ath9k/ar9002_phy.c

+6 −10
Original line number Diff line number Diff line
@@ -455,16 +455,12 @@ static u32 ar9002_hw_compute_pll_control(struct ath_hw *ah, 
		pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);



	if (chan && IS_CHAN_5GHZ(chan)) {

		pll |= SM(0x28, AR_RTC_9160_PLL_DIV);





		if (AR_SREV_9280_20(ah)) {

			if (((chan->channel % 20) == 0)

			    || ((chan->channel % 10) == 0))

		if (IS_CHAN_A_FAST_CLOCK(ah, chan))

			pll = 0x142c;

		else if (AR_SREV_9280_20(ah))

			pll = 0x2850;

		else

				pll = 0x142c;

		}

			pll |= SM(0x28, AR_RTC_9160_PLL_DIV);

	} else {

		pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);

	}

drivers/net/wireless/ath/ath9k/ar9003_phy.c

+2 −2
Original line number Diff line number Diff line
@@ -583,7 +583,7 @@ static int ar9003_hw_process_ini(struct ath_hw *ah, 
	 * For 5GHz channels requiring Fast Clock, apply

	 * different modal values.

	 */

	if (IS_CHAN_A_5MHZ_SPACED(chan))

	if (IS_CHAN_A_FAST_CLOCK(ah, chan))

		REG_WRITE_ARRAY(&ah->iniModesAdditional,

				modesIndex, regWrites);
@@ -613,7 +613,7 @@ static void ar9003_hw_set_rfmode(struct ath_hw *ah, 
	rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))

		? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;



	if (IS_CHAN_A_5MHZ_SPACED(chan))

	if (IS_CHAN_A_FAST_CLOCK(ah, chan))

		rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);



	REG_WRITE(ah, AR_PHY_MODE, rfMode);

drivers/net/wireless/ath/ath9k/hw.c

+6 −2
Original line number Diff line number Diff line
@@ -1228,8 +1228,7 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, 
	    (chan->channel != ah->curchan->channel) &&

	    ((chan->channelFlags & CHANNEL_ALL) ==

	     (ah->curchan->channelFlags & CHANNEL_ALL)) &&

	     !(AR_SREV_9280(ah) || IS_CHAN_A_5MHZ_SPACED(chan) ||

	     IS_CHAN_A_5MHZ_SPACED(ah->curchan))) {

	    !AR_SREV_9280(ah)) {



		if (ath9k_hw_channel_change(ah, chan)) {

			ath9k_hw_loadnf(ah, ah->curchan);
@@ -2202,6 +2201,11 @@ int ath9k_hw_fill_cap_info(struct ath_hw *ah) 
		pCap->txs_len = sizeof(struct ar9003_txs);

	} else {

		pCap->tx_desc_len = sizeof(struct ath_desc);

		if (AR_SREV_9280_20(ah) &&

		    ((ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) <=

		      AR5416_EEP_MINOR_VER_16) ||

		     ah->eep_ops->get_eeprom(ah, EEP_FSTCLK_5G)))

			pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK;

	}



	if (AR_SREV_9300_20_OR_LATER(ah))

drivers/net/wireless/ath/ath9k/hw.h

+2 −3
Original line number Diff line number Diff line
@@ -369,10 +369,9 @@ struct ath9k_channel { 
#define IS_CHAN_2GHZ(_c) (((_c)->channelFlags & CHANNEL_2GHZ) != 0)

#define IS_CHAN_HALF_RATE(_c) (((_c)->channelFlags & CHANNEL_HALF) != 0)

#define IS_CHAN_QUARTER_RATE(_c) (((_c)->channelFlags & CHANNEL_QUARTER) != 0)

#define IS_CHAN_A_5MHZ_SPACED(_c)			\

#define IS_CHAN_A_FAST_CLOCK(_ah, _c)			\

	((((_c)->channelFlags & CHANNEL_5GHZ) != 0) &&	\

	 (((_c)->channel % 20) != 0) &&			\

	 (((_c)->channel % 10) != 0))

	 ((_ah)->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK))



/* These macros check chanmode and not channelFlags */

#define IS_CHAN_B(_c) ((_c)->chanmode == CHANNEL_B)