Merge tag 'for-3.16' of...

		compatible = "samsung,exynos-sataphy-i2c";

		reg = <0x38>;

	};

Samsung Exynos5 SoC series USB DRD PHY controller

--------------------------------------------------

Required properties:

- compatible : Should be set to one of the following supported values:

	- "samsung,exynos5250-usbdrd-phy" - for exynos5250 SoC,

	- "samsung,exynos5420-usbdrd-phy" - for exynos5420 SoC.

- reg : Register offset and length of USB DRD PHY register set;

- clocks: Clock IDs array as required by the controller

- clock-names: names of clocks correseponding to IDs in the clock property;

	       Required clocks:

	- phy: main PHY clock (same as USB DRD controller i.e. DWC3 IP clock),

	       used for register access.

	- ref: PHY's reference clock (usually crystal clock), used for

	       PHY operations, associated by phy name. It is used to

	       determine bit values for clock settings register.

	       For Exynos5420 this is given as 'sclk_usbphy30' in CMU.

- samsung,pmu-syscon: phandle for PMU system controller interface, used to

		      control pmu registers for power isolation.

- #phy-cells : from the generic PHY bindings, must be 1;

For "samsung,exynos5250-usbdrd-phy" and "samsung,exynos5420-usbdrd-phy"

compatible PHYs, the second cell in the PHY specifier identifies the

PHY id, which is interpreted as follows:

  0 - UTMI+ type phy,

  1 - PIPE3 type phy,

Example:

	usbdrd_phy: usbphy@12100000 {

		compatible = "samsung,exynos5250-usbdrd-phy";

		reg = <0x12100000 0x100>;

		clocks = <&clock 286>, <&clock 1>;

		clock-names = "phy", "ref";

		samsung,pmu-syscon = <&pmu_system_controller>;

		#phy-cells = <1>;

	};

- aliases: For SoCs like Exynos5420 having multiple USB 3.0 DRD PHY controllers,

	   'usbdrd_phy' nodes should have numbered alias in the aliases node,

	   in the form of usbdrdphyN, N = 0, 1... (depending on number of

	   controllers).

Example:

	aliases {

		usbdrdphy0 = &usb3_phy0;

		usbdrdphy1 = &usb3_phy1;

	};

-----------------------

Required properties:

- compatible : should be one of "allwinner,sun4i-a10-usb-phy",

  "allwinner,sun5i-a13-usb-phy" or "allwinner,sun7i-a20-usb-phy"

- compatible : should be one of

  * allwinner,sun4i-a10-usb-phy

  * allwinner,sun5i-a13-usb-phy

  * allwinner,sun6i-a31-usb-phy

  * allwinner,sun7i-a20-usb-phy

- reg : a list of offset + length pairs

- reg-names : "phy_ctrl", "pmu1" and for sun4i or sun7i "pmu2"

- reg-names :

  * "phy_ctrl"

  * "pmu1"

  * "pmu2" for sun4i, sun6i or sun7i

- #phy-cells : from the generic phy bindings, must be 1

- clocks : phandle + clock specifier for the phy clock

- clock-names : "usb_phy"

- clocks : phandle + clock specifier for the phy clocks

- clock-names :

  * "usb_phy" for sun4i, sun5i or sun7i

  * "usb0_phy", "usb1_phy" and "usb2_phy" for sun6i

- resets : a list of phandle + reset specifier pairs

- reset-names : "usb0_reset", "usb1_reset" and for sun4i or sun7i "usb2_reset"

- reset-names :

  * "usb0_reset"

  * "usb1_reset"

  * "usb2_reset" for sun4i, sun6i or sun7i

Example:

	usbphy: phy@0x01c13400 {

 - reg : Address and length of the register set for the device.

 - #phy-cells: determine the number of cells that should be given in the

   phandle while referencing this phy.

 - clocks: a list of phandles and clock-specifier pairs, one for each entry in

   clock-names.

 - clock-names: should include:

   * "wkupclk" - wakeup clock.

   * "refclk" - reference clock (optional).

Optional properties:

 - ctrl-module : phandle of the control module used by PHY driver to power on

	reg = <0x4a0ad080 0x58>;

	ctrl-module = <&omap_control_usb>;

	#phy-cells = <0>;

	clocks = <&usb_phy_cm_clk32k>, <&usb_otg_ss_refclk960m>;

	clock-names = "wkupclk", "refclk";

};

TI PIPE3 PHY

config BCM_KONA_USB2_PHY

	tristate "Broadcom Kona USB2 PHY Driver"

	depends on GENERIC_PHY

	depends on HAS_IOMEM

	select GENERIC_PHY

	help

	  Enable this to support the Broadcom Kona USB 2.0 PHY.

	  particular SoC is compiled in the driver. In case of Exynos 5250 four

	  phys are available - device, host, HSIC0 and HSIC.

config PHY_EXYNOS5_USBDRD

	tristate "Exynos5 SoC series USB DRD PHY driver"

	depends on ARCH_EXYNOS5 && OF

	depends on HAS_IOMEM

	select GENERIC_PHY

	select MFD_SYSCON

	help

	  Enable USB DRD PHY support for Exynos 5 SoC series.

	  This driver provides PHY interface for USB 3.0 DRD controller

	  present on Exynos5 SoC series.

config PHY_XGENE

	tristate "APM X-Gene 15Gbps PHY support"

	depends on HAS_IOMEM && OF && (ARM64 || COMPILE_TEST)

phy-exynos-usb2-$(CONFIG_PHY_EXYNOS4210_USB2)	+= phy-exynos4210-usb2.o

phy-exynos-usb2-$(CONFIG_PHY_EXYNOS4X12_USB2)	+= phy-exynos4x12-usb2.o

phy-exynos-usb2-$(CONFIG_PHY_EXYNOS5250_USB2)	+= phy-exynos5250-usb2.o

obj-$(CONFIG_PHY_EXYNOS5_USBDRD)	+= phy-exynos5-usbdrd.o

obj-$(CONFIG_PHY_XGENE)			+= phy-xgene.o