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Commit 6a4ccd9a authored by Beniamino Galvani's avatar Beniamino Galvani Committed by Carlo Caione
Browse files

ARM: meson: enable L2 cache 



This enables the L2 cache controller available in Amlogic SoCs.

Signed-off-by: default avatarBeniamino Galvani <b.galvani@gmail.com>
Acked-by: default avatarArnd Bergmann <arnd@arndb.de>
Signed-off-by: default avatarCarlo Caione <carlo@caione.org>
parent a25a6772

arch/arm/mach-meson/Kconfig

+1 −0
Original line number Original line Diff line number Diff line
@@ -2,6 +2,7 @@ menuconfig ARCH_MESON 
	bool "Amlogic Meson SoCs" if ARCH_MULTI_V7

	bool "Amlogic Meson SoCs" if ARCH_MULTI_V7

	select GENERIC_IRQ_CHIP

	select GENERIC_IRQ_CHIP

	select ARM_GIC

	select ARM_GIC

	select CACHE_L2X0





if ARCH_MESON

if ARCH_MESON

arch/arm/mach-meson/meson.c

+2 −0
Original line number Original line Diff line number Diff line
@@ -24,4 +24,6 @@ static const char * const meson_common_board_compat[] = { 




DT_MACHINE_START(MESON, "Amlogic Meson platform")

DT_MACHINE_START(MESON, "Amlogic Meson platform")

	.dt_compat	= meson_common_board_compat,

	.dt_compat	= meson_common_board_compat,

	.l2c_aux_val	= 0,

	.l2c_aux_mask	= ~0,

MACHINE_END
 
MACHINE_END