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Commit 69f9cdc6 authored by Masahiro Yamada's avatar Masahiro Yamada
Browse files

ARM: dts: uniphier: add Denali NAND controller node



Add NAND controller node to LD4, Pro4, sLD8, Pro5, and PXs2.
Set up pinctrl to enable 2 chip select lines except Pro4.  The CS1
for Pro4 is multiplexed with other peripherals such as UART2, so
I did not enable it.

Signed-off-by: default avatarMasahiro Yamada <yamada.masahiro@socionext.com>
parent ed8bc76b
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+4 −0
Original line number Original line Diff line number Diff line
@@ -64,3 +64,7 @@
&usb1 {
&usb1 {
	status = "okay";
	status = "okay";
};
};

&nand {
	status = "okay";
};
+11 −0
Original line number Original line Diff line number Diff line
@@ -285,6 +285,17 @@
				#reset-cells = <1>;
				#reset-cells = <1>;
			};
			};
		};
		};

		nand: nand@68000000 {
			compatible = "socionext,uniphier-denali-nand-v5a";
			status = "disabled";
			reg-names = "nand_data", "denali_reg";
			reg = <0x68000000 0x20>, <0x68100000 0x1000>;
			interrupts = <0 65 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_nand2cs>;
			clocks = <&sys_clk 2>;
		};
	};
	};
};
};


+4 −0
Original line number Original line Diff line number Diff line
@@ -58,3 +58,7 @@
&i2c0 {
&i2c0 {
	status = "okay";
	status = "okay";
};
};

&nand {
	status = "okay";
};
+4 −0
Original line number Original line Diff line number Diff line
@@ -66,3 +66,7 @@
&usb3 {
&usb3 {
	status = "okay";
	status = "okay";
};
};

&nand {
	status = "okay";
};
+11 −0
Original line number Original line Diff line number Diff line
@@ -305,6 +305,17 @@
				#reset-cells = <1>;
				#reset-cells = <1>;
			};
			};
		};
		};

		nand: nand@68000000 {
			compatible = "socionext,uniphier-denali-nand-v5a";
			status = "disabled";
			reg-names = "nand_data", "denali_reg";
			reg = <0x68000000 0x20>, <0x68100000 0x1000>;
			interrupts = <0 65 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_nand>;
			clocks = <&sys_clk 2>;
		};
	};
	};
};
};


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