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Commit 697c4078 authored by Clint Taylor's avatar Clint Taylor Committed by Daniel Vetter
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drm/i915/hdmi: Enable pipe pixel replication for SD interlaced modes 



Enable 2x pixel replication for modes the mode flag DBLCLK to double
horizontal timings and pixel clock across TMDS.

Signed-off-by: default avatarClint Taylor <clinton.a.taylor@intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent fb01d280

drivers/gpu/drm/i915/intel_hdmi.c

+12 −3
Original line number Diff line number Diff line
@@ -864,10 +864,15 @@ static enum drm_mode_status 
intel_hdmi_mode_valid(struct drm_connector *connector,

		      struct drm_display_mode *mode)

{

	if (mode->clock > hdmi_portclock_limit(intel_attached_hdmi(connector),

	int clock = mode->clock;



	if (mode->flags & DRM_MODE_FLAG_DBLCLK)

		clock *= 2;



	if (clock > hdmi_portclock_limit(intel_attached_hdmi(connector),

					 true))

		return MODE_CLOCK_HIGH;

	if (mode->clock < 20000)

	if (clock < 20000)

		return MODE_CLOCK_LOW;



	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
@@ -921,6 +926,10 @@ bool intel_hdmi_compute_config(struct intel_encoder *encoder, 
			intel_hdmi->color_range = 0;

	}



	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) {

		pipe_config->pixel_multiplier = 2;

	}



	if (intel_hdmi->color_range)

		pipe_config->limited_color_range = true;