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Commit 692c4e42 authored by Nate Watterson's avatar Nate Watterson Committed by Will Deacon
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iommu/arm-smmu-v3: limit use of 2-level stream tables 



In the current arm-smmu-v3 driver, all smmus that support 2-level
stream tables are being forced to use them. This is suboptimal for
smmus that support fewer stream id bits than would fill in a single
second level table. This patch limits the use of 2-level tables to
smmus that both support the feature and whose first level table can
possibly contain more than a single entry.

Signed-off-by: default avatarNate Watterson <nwatters@codeaurora.org>
Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
parent 810871c5

drivers/iommu/arm-smmu-v3.c

+10 −11
Original line number Diff line number Diff line
@@ -1977,17 +1977,9 @@ static int arm_smmu_init_strtab_2lvl(struct arm_smmu_device *smmu) 
	u32 size, l1size;

	struct arm_smmu_strtab_cfg *cfg = &smmu->strtab_cfg;



	/*

	 * If we can resolve everything with a single L2 table, then we

	 * just need a single L1 descriptor. Otherwise, calculate the L1

	 * size, capped to the SIDSIZE.

	 */

	if (smmu->sid_bits < STRTAB_SPLIT) {

		size = 0;

	} else {

	/* Calculate the L1 size, capped to the SIDSIZE. */

	size = STRTAB_L1_SZ_SHIFT - (ilog2(STRTAB_L1_DESC_DWORDS) + 3);

	size = min(size, smmu->sid_bits - STRTAB_SPLIT);

	}

	cfg->num_l1_ents = 1 << size;



	size += STRTAB_SPLIT;
@@ -2498,6 +2490,13 @@ static int arm_smmu_device_hw_probe(struct arm_smmu_device *smmu) 
	smmu->ssid_bits = reg >> IDR1_SSID_SHIFT & IDR1_SSID_MASK;

	smmu->sid_bits = reg >> IDR1_SID_SHIFT & IDR1_SID_MASK;



	/*

	 * If the SMMU supports fewer bits than would fill a single L2 stream

	 * table, use a linear table instead.

	 */

	if (smmu->sid_bits <= STRTAB_SPLIT)

		smmu->features &= ~ARM_SMMU_FEAT_2_LVL_STRTAB;



	/* IDR5 */

	reg = readl_relaxed(smmu->base + ARM_SMMU_IDR5);